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PDF APE8902C Data sheet ( Hoja de datos )
| Número de pieza | APE8902C | |
| Descripción | 2A ULTRA LOW DROPOUT LINEAR REGULATOR | |
| Fabricantes | Advanced Power Electronics | |
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Advanced Power
Electronics Corp.
APE8902C
2A ULTRA LOW DROPOUT LINEAR REGULATOR
FEATURES
Ultra Low Dropout 0.21V(typical) @ 2A Output
Current for 1.2V Output Voltage
Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
EN Pull-low for APE8902CMP-A
EN Pull-high for APE8902CMP-B
Fast Transient Response
Adjustable Output Voltage by External Resistors
Power-On-Reset Monitoring on Both VCNTL
and VIN Pins
Internal Soft-Start
Current-Limit and Thermal Shutdown Protection
Power-OK Output with a Delay Time
SO-8 with Exposed Pad & DFN 3x3-10L
Pb-Free Package.
Halogen Free Product
TYPICAL APPLICATION
DESCRIPTION
The APE8902C series is a 2A ultra low dropout linear
regulator. This product is specifically designed to provide
well supply voltage for front-side-bus termination on
motherboards and NB applications. The IC needs two
supply voltages, a control voltage for the circuitry and a
main supply voltage for power conversion, to reduce power
dissipation and provide extremely low dropout. The
APE8902C series integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages to
prevent wrong operations. A thermal shutdown and current
limit functions protect the device against thermal and
current over-loads. A POK indicates the output status with
time delay which is set internally. It can control other
converter for power sequence.
The APE8902C series can be enabled by other power
system. Pulling and holding the EN pin below 0.4V shuts off
the output.
The APE8902C series is available in ESOP-8 package
which features small size as SO-8 and an Exposed Pad to
reduce the junction-to-case resistance, being applicable in
2~3W applications.
VCNTL
POK U1
R3
POK
10k
EN EN
GND
ADJ
VIN VIN VOUT
C1
4 .7 uF
VCNTL
C2
1 uF
APE8902C
NC
VOUT
R 1 CF
20k *option
Cout
10uF
R2
10k
Data and specifications subject to change without notice
1
20130206V4.1
1 page  
Advanced Power
Electronics Corp.
APE8902C
PIN DESCRIPTION
FB
Connecting this pin to an external resistor divider receives the feedback voltage of the
regulator. The output voltage set by the resistor divider is determined by:
Where R1 is connected from VOUT to FB with Kelvin sensing and R2 is connected from FB
to GND. A bypass capacitor may be connected with R1 in parallel to improve load transient
response. The R2 range in 1K~4.7KΩ for AL output capacitor and 30K~100KΩ for MLCC output
capacitor are recommended.
VIN
Main supply input pins for power conversions. The voltage at this pin is monitored for Power-
On Reset purpose.
VCNTL
Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply
voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-
On Reset purpose.
POK
Power-OK signal output pin. This pin is an open-drain output used to indicate status of
output voltage by sensing FB voltage. This pin is pulled low when the rising FB voltage is not
above the VPOK threshold or the falling FB voltage is below the VPOK threshold, indicating the
output is not OK.
EN
Enable control pin. Pulling and holding this pin below 0.4V shuts down the output. When re-
enabled, the IC undergoes a new soft-start cycle. For APE8902CMP-B, this pin is internal pulled
up to VCNTL voltage, enabling the regulator. For APE8902CMP-A, this pin is internal pulled down
to GND voltage, shutdown the regulator. The pull-high current is 10uA (typ.)
VOUT
Output of the regulator. Please connect Pin 6 using wide tracks. It is necessary to connect
an output capacitor with this pin for closed-loop compensation and improving transient responses.
FUNCTION DESCRIPTION
Power-On-Reset
A Power-On-Reset (POR) circuit monitors both input voltages at VCNTL and VIN pins to
prevent wrong logic controls. The POR function initiates a soft-start process after the two supply
voltages exceed their rising POR threshold voltages during powering on. The POR function also
pulls low the POK pin regardless the output voltage when the VCNTL voltage falls below its falling
POR threshold.
Internal Soft-Start
An internal soft-start function controls rise rate of the output voltage to limit the current surge
at start-up. The typical soft-start interval is about 0.2ms.
Output Voltage Regulation
An error amplifier working with a temperature compensated 0.8V reference and an output
NMOS regulates output to the preset voltage. The error amplifier designed with high bandwidth
and DC gain provides very fast transient response and less load regulation. It compares the
reference with the feedback voltage and amplifies the difference to drive the output NMOS which
provides load current from VIN to VOUT.
5
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| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet APE8902C.PDF ] | |
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