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PDF ADN8834 Data sheet ( Hoja de datos )
| Número de pieza | ADN8834 | |
| Descripción | 1.5A Thermoelectric Cooler (TEC) Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Ultracompact, 1.5 A Thermoelectric Cooler
(TEC) Controller
ADN8834
FEATURES
Patented high efficiency single inductor architecture
Integrated low RDSON MOSFETs for the TEC controller
TEC voltage and current operation monitoring
No external sense resistor required
Independent TEC heating and cooling current limit settings
Programmable maximum TEC voltage
2.0 MHz PWM driver switching frequency
External synchronization
Two integrated, zero drift, rail-to-rail chopper amplifiers
Capable of NTC or RTD thermal sensors
2.50 V reference output with 1% accuracy
Temperature lock indicator
Available in a 25-ball, 2.5 mm × 2.5 mm WLCSP or in a
24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
TEC temperature control
Optical modules
Optical fiber amplifiers
Optical networking systems
Instruments requiring TEC temperature control
GENERAL DESCRIPTION
The ADN8834 is a monolithic TEC controller with an integrated
TEC controller. It has a linear power stage, a pulse-width
modulation (PWM) power stage, and two zero-drift, rail-to-rail
operational amplifiers. The linear controller works with the PWM
driver to control the internal power MOSFETs in an H-bridge
configuration. By measuring the thermal sensor feedback
voltage and using the integrated operational amplifiers as a
proportional integral differential (PID) compensator to condition
the signal, the ADN8834 drives current through a TEC to settle
the temperature of a laser diode or a passive component attached
to the TEC module to the programmed target temperature.
The ADN8834 supports negative temperature coefficient (NTC)
thermistors as well as positive temperature coefficient (PTC)
resistive temperature detectors (RTD). The target temperature is
set as an analog voltage input either from a digital-to-analog
converter (DAC) or from an external resistor divider.
IN1P
IN1N
OUT1
IN2P
IN2N
OUT2
FUNCTIONAL BLOCK DIAGRAM
VLIM/
VDD SD ILIM VTEC ITEC
PVIN
ERROR
AMP
TEC CURRENT
AND VOLTAGE
SENSE AND LIMIT
COMP
AMP
CONTROLLER
TEC DRIVER
LINEAR
POWER
STAGE
PWM
POWER
STAGE
LDR
SW
SFB
VOLTAGE
REFERENCE
OSCILLATOR
AGND
VREF
EN/SY
Figure 1.
PGNDx
The temperature control loop of the ADN8834 is stabilized by
PID compensation utilizing the built in, zero drift chopper
amplifiers. The internal 2.50 V reference voltage provides a 1%
accurate output that is used to bias a thermistor temperature
sensing bridge as well as a voltage divider network to program
the maximum TEC current and voltage limits for both the heating
and cooling modes. With the zero drift chopper amplifiers,
extremely good long-term temperature stability is maintained via
an autonomous analog temperature control loop.
Table 1. TEC Family Models
Device No. MOSFET Thermal Loop
ADN8831 Discrete Digital/analog
ADN8833 Integrated Digital
ADN8834 Integrated Digital/analog
Package
LFCSP (CP-32-7)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
WLCSP (CB-25-7),
LFCSP (CP-24-15)
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADN8834
Parameter
N-MOSFET
Leakage Current
P-MOSFET
N-MOSFET
SW Node Rise Time1
PWM Duty Cycle2
SFB Input Bias Current
PWM OSCILLATOR
Internal Oscillator Frequency
EN/SY Input Voltage
Low
High
External Synchronization Frequency
Synchronization Pulse Duty Cycle
EN/SY Rising to PWM Rising Delay
EN/SY to PWM Lock Time
EN/SY Input Current
Pull-Down Current
ERROR/COMPENSATION AMPLIFIERS
Input Offset Voltage
Input Voltage Range
Common-Mode Rejection Ratio (CMRR)
Output Voltage
High
Symbol
RDS_NS(ON)
ISW_P_LKG
ISW_N_LKG
tSW_R
DSW
ISFB
fOSC
VEN/SY_ILOW
VEN/SY_IHIGH
fSYNC
DSYNC
tSYNC_PWM
tSY_LOCK
IEN/SY
VOS1
VOS2
VCM1, VCM2
CMRR1, CMRR2
VOH1, VOH2
Test Conditions/Comments
WLCSP, VPVIN = 5.0 V
WLCSP, VPVIN = 3.3 V
LFCSP, VPVIN = 5.0 V
LFCSP, VPVIN = 3.3 V
CSW = 1 nF
EN/SY high
Number of SYNC cycles
VCM1 = 1.5 V, VOS1 = VIN1P − VIN1N
VCM2 = 1.5 V, VOS2 = VIN2P − VIN2N
VCM1, VCM2 = 0.2 V to VVDD − 0.2 V
Low
Power Supply Rejection Ratio (PSRR)
Output Current
Gain Bandwidth Product1
TEC CURRENT LIMIT
ILIM Input Voltage Range
Cooling
VOL1, VOL2
PSRR1, PSRR2
IOUT1, IOUT2
GBW1, GBW2
Sourcing and sinking
VOUT1,VOUT2 = 0.5 V to VVDD − 1 V
VILIMC
Heating
Current-Limit Threshold
Cooling
Heating
ILIM Input Current
Heating
Cooling
Cooling to Heating Current Detection
Threshold
TEC VOLTAGE LIMIT
Voltage Limit Gain
VLIM/SD Input Voltage Range1
VLIM/SD Input Current
Cooling
Heating
VILIMH
VILIMC_TH
VILIMH_TH
IILIMH
IILIMC
ICOOL_HEAT_TH
AVLIM
VVLIM
IILIMC
IILIMH
VITEC = 0.5 V
VITEC = 2 V
Sourcing current
(VDRL − VSFB)/VVLIM
VOUT2 < VVREF/2
VOUT2 > VVREF/2, sinking current
Min Typ
40
45
45
55
0.1
0.1
1
6
1
1.85 2.0
2.1
1.85
10
50
0.3
0.3
10
10
0
120
VVDD −
0.04
120
5
2
1.3
0.2
1.98 2.0
0.48 0.5
−0.2
37.5 40
40
2
0.2
−0.2
8 10
Rev. A | Page 4 of 27
Data Sheet
Max Unit
60 mΩ
65 mΩ
75 mΩ
85 mΩ
10 µA
10 µA
ns
93 %
2 µA
2.15 MHz
0.8 V
V
3.25 MHz
90 %
ns
10 Cycles
0.5 µA
0.5 µA
100 µV
100 µV
VVDD
V
dB
V
10 mV
dB
mA
MHz
VVREF −
0.2
1.2
2.02
0.52
+0.2
42.5
V
V
V
V
µA
µA
mA
VVDD/2
+0.2
12.2
V/V
V
µA
µA
5 Page 
ADN8834
20
15
VVIINN
=
=
3.3V
5V
10
5
0
–5
–10
–15
–20
0.5
1.0 1.5 2.0
TEC VOLTAGE (V)
2.5
Figure 16. VTEC Voltage Reading Error vs. TEC Voltage in Cooling Mode
20
VVIINN
=
=
3.3V
5V
15
10
5
0
–5
–10
–15
–20
–2.5 –2.0 –1.5 –1.0 –0.5
TEC VOLTAGE (V)
Figure 17. VTEC Voltage Reading Error vs. TEC Voltage in Heating Mode
LDO (TEC+)
PWM (TEC–)
TEC CURRENT
4
1
CH1 500mV BW CH2 500mV BW M200ms A CH4 –108mA
CH4 200mA Ω BW
T –28.000ms
Figure 18. Cooling to Heating Transition
Data Sheet
TEC CURRENT
4
PWM (TEC–)
LDO (TEC+)
1
CH1 500mV BW CH2 500mV BW M10ms
A CH4 –8mA
CH3 300mA Ω BW
T 5.4ms
Figure 19. Zero Crossing TEC Current Zoom in from Heating to Cooling
TEC CURRENT
4
PWM (TEC–)
LDO (TEC+)
1
CH1 500mV BW CH2 500mV BW M10ms
A CH4 12mA
CH3 200mA Ω BW
T 5.4ms
Figure 20. Zero Crossing TEC Current Zoom in from Cooling to Heating
EN
3
TEC CURRENT
4
LDO (TEC–)
PWM (TEC+)
1
CH1 1V BW CH2 1V BW CH3 2V BW M20.0ms A CH3
CH4 500mA Ω BW
T 40ms
800mV
Figure 21. Typical Enable Waveforms in Cooling Mode,
VIN = 3.3 V, Load = 2 Ω, TEC Current = 1 A
Rev. A | Page 10 of 27
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet ADN8834.PDF ] | |
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