ADuM240D Datasheet PDF ( Pinout ) - 5.0 kV rms Quad Digital Isolators

ADuM240D Datasheet PDF - Analog Devices

Part Number	*ADuM240D*
Description	5.0 kV rms Quad Digital Isolators
Manufacturers	Analog Devices
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5.0 kV rms Quad Digital Isolators

Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E

FEATURES

High common-mode transient immunity: 100 kV/μs

High robustness to radiated and conducted noise

Low propagation delay

13 ns maximum for 5 V operation

15 ns maximum for 1.8 V operation

150 Mbps maximum guaranteed data rate

Safety and regulatory approvals (pending)

UL recognition: 5000 V rms for 1 minute per UL 1577

CSA Component Acceptance Notice 5A

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

VIORM = 849 V peak

8000 V peak reinforced surge isolation voltage

CQC certification per GB4943.1-2011

Backward compatibility

ADuM240E1/ADuM241E1/ADuM242E1 pin compatible

with ADuM2400/ADuM2401/ADuM2402

Low dynamic power consumption

1.8 V to 5 V level translation

High temperature operation: 125°C

Fail-safe high or low options

16-lead, RoHS compliant, SOIC package

Qualified for automotive applications

APPLICATIONS

General-purpose multichannel isolation

Serial peripheral interface (SPI)/data converter isolation

Industrial field bus isolation

GENERAL DESCRIPTION

The ADuM240D/ADuM240E/ADuM241D/ADuM241E/

ADuM242D/ADuM242E1 are quad-channel digital isolators

based on Analog Devices, Inc., iCoupler® technology. Combining

high speed, complementary metal-oxide semiconductor (CMOS)

and monolithic air core transformer technology, these isolation

components provide outstanding performance characteristics

superior to alternatives such as optocoupler devices and other

integrated couplers. The maximum propagation delay is 13 ns

with a pulse width distortion of less than 3 ns at 5 V operation.

Channel matching is tight at 3.0 ns maximum.

The ADuM240D/ADuM240E/ADuM241D/ADuM241E/

ADuM242D/ADuM242E data channels are independent and

are available in a variety of configurations with a withstand

voltage rating of 5.0 kV rms (see the Ordering Guide). The

devices operate with the supply voltage on either side ranging

from 1.8 V to 5 V, providing compatibility with lower voltage

FUNCTIONAL BLOCK DIAGRAMS

VDD1 1 ADuM240D/ADuM240E 16 VDD2

GND1 2

VIA 3

ENCODE

DECODE

15 GND2

14 VOA

VIB 4

ENCODE

DECODE

13 VOB

VIC 5

ENCODE

DECODE

12 VOC

VID 6

ENCODE

DECODE

11 VOD

DISABLE1/NIC 7

GND1 8

10 NIC/VE2

9 GND2

NOTES

1. NIC = NO INTERNAL CONNECTION. LEAVE THIS PIN FLOATING.

2. PIN 7 IS DISABLE1 AND PIN 10 IS NIC FOR THE ADuM240D, AND

PIN 7 IS NIC AND PIN 10 IS VE2 FOR THE ADuM240E.

Figure 1. ADuM240D/ADuM240E Functional Block Diagram

VDD1 1 ADuM241D/ADuM241E 16 VDD2

GND1 2

VIA 3

ENCODE

DECODE

15 GND2

14 VOA

VIB 4

ENCODE

DECODE

13 VOB

VIC 5

ENCODE

DECODE

12 VOC

VOD 6

DECODE

ENCODE

11 VID

DISABLE1/VE1 7

GND1 8

10 DISABLE2/VE2

9 GND2

NOTES

1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM241D,

AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM241E.

Figure 2. ADuM241D/ADuM241E Functional Block Diagram

VDD1 1

GND1 2

VIA 3

ADuM242D/ADuM242E

ENCODE

DECODE

16 VDD2

15 GND2

14 VOA

VIB 4

ENCODE

DECODE

13 VOB

VOC 5

DECODE

ENCODE

12 VIC

VOD 6

DECODE

ENCODE

11 VID

DISABLE1/VE1 7

GND1 8

10 DISABLE2/VE2

9 GND2

NOTES

1. PIN 7 IS DISABLE1 AND PIN 10 IS DISABLE2 FOR THE ADuM242D,

AND PIN 7 IS VE1 AND PIN 10 IS VE2 FOR THE ADuM242E.

Figure 3. ADuM242D/ADuM242E Functional Block Diagram

systems as well as enabling voltage translation functionality

across the isolation barrier.

Unlike other optocoupler alternatives, dc correctness is ensured in

the absence of input logic transitions. Two different fail-safe options

are available by which the outputs transition to a predetermined

state when the input power supply is not applied or the inputs are

disabled. The ADuM240E1/ADuM241E1/ ADuM242E1 are pin

compatible with the ADuM2400/ ADuM2401/ADuM2402.

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.

Rev. A

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Data Sheet ADuM240D/ADuM240E/ADuM241D/ADuM241E/ADuM242D/ADuM242E

ELECTRICAL CHARACTERISTICS—3.3 V OPERATION

All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended

operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications

are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Supply currents are specified with 50% duty cycle signals.

Table 3.

Parameter

SWITCHING SPECIFICATIONS

Pulse Width

Data Rate1

Propagation Delay

Pulse Width Distortion

Change vs. Temperature

Propagation Delay Skew

Channel Matching

Codirectional

Opposing Direction

Jitter

DC SPECIFICATIONS

Input Threshold Voltage

Logic High

Logic Low

Output Voltage

Logic High

Logic Low

Input Current per Channel

VE2 Enable Input Pull-Up Current

DISABLE1 Input Pull-Down Current

Tristate Output Current per Channel

Quiescent Supply Current

ADuM240D/ADuM240E

ADuM241D/ADuM241E

ADuM242D/ADuM242E

Dynamic Supply Current

Dynamic Input

Dynamic Output

Symbol Min

Typ Max Unit

Test Conditions/Comments

PW 6.6

ns Within PWD limit

150

Mbps

Within PWD limit

tPHL, tPLH 4.8

6.8 14

50% input to 50% output

PWD

0.7 3 ns |tPLH − tPHL|

1.5 ps/°C

tPSK

7.5 ns

Between any two units at the same

temperature, voltage, and load

tPSKCD

tPSKOD

0.7 3.0

580

120

ps p-p

ps rms

See the Jitter Measurement section

VIH 0.7 × VDDx

VIL

0.3 × VDDx V

VOH VDDx − 0.1 VDDx

VDDx − 0.4 VDDx − 0.2

VOL 0.0 0.1

0.2 0.4

−10

+0.01

+10

IPU −10 −3

IPD 9 15

IOZ

−10

+0.01

+10

μA

IOx2 = −20 μA, VIx = VIxH3

IOx2 = −2 mA, VIx = VIxH3

IOx2 = 20 μA, VIx = VIxL4

IOx2 = 2 mA, VIx = VIxL4

0 V ≤ VIx ≤ VDDx

VE2 = 0 V

DISABLE1 = VDDx

0 V ≤ VOx ≤ VDDx

IDD1 (Q)

IDD2 (Q)

IDD1 (Q)

IDD2 (Q)

IDD1 (Q)

IDD2 (Q)

IDD1 (Q)

IDD2 (Q)

IDD1 (Q)

IDD2 (Q)

IDD1 (Q)

IDD2 (Q)

IDDI (D)

IDDO (D)

1.2 2.12 mA

2.0 2.68 mA

12.0 19.6 mA

2.0 2.8 mA

VI5 = 0 (E0, D0), 1 (E1, D1)6

VI5 = 1 (E0, D0), 0 (E1, D1)6

1.5 2.36 mA

1.8 2.52 mA

9.8 16.7 mA

5.7 9.7 mA

VI5 = 0 (E0, D0), 1 (E1, D1)6

VI5 = 1 (E0, D0), 0 (E1, D1)6

1.6 2.4 mA

7.0 11.2 mA

VI5 = 0 (E0, D0), 1 (E1, D1)6

VI5 = 1 (E0, D0), 0 (E1, D1)6

0.01 mA/Mbps Inputs switching, 50% duty cycle

Rev. A | Page 5 of 26

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ADuM240D Datasheet PDF - Analog Devices

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