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PDF ISL70002SEH Data sheet ( Hoja de datos )
| Número de pieza | ISL70002SEH | |
| Descripción | Radiation Hardened and SEE Hardened 12A Synchronous Buck Regulator | |
| Fabricantes | Intersil | |
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DATASHEET
Radiation Hardened and SEE Hardened 12A
Synchronous Buck Regulator with Current Sharing
ISL70002SEH
The ISL70002SEH is a radiation hardened and SEE hardened
high efficiency monolithic synchronous buck regulator with
integrated MOSFETs. This single chip power solution operates
over an input voltage range of 3V to 5.5V and provides a
tightly regulated output voltage that is externally adjustable
from 0.8V to ~85% of the input voltage. Output load current
capacity is 12A for TJ ≤ +150°C. The two ISL70002SEH
devices configured to current share can provide 19A total
output current, assuming ±27% worst-case current share
accuracy.
The ISL70002SEH utilizes peak current-mode control with
integrated error amp compensation and pin selectable slope
compensation. Switching frequency is also pin selectable to
either 1MHz or 500kHz. Two devices can be synchronized
180° out-of-phase to reduce input RMS ripple current.
High integration makes the ISL70002SEH an ideal choice to
power small form factor applications. Two devices can be
synchronized to provide a complete power solution for large
scale digital ICs, like field programmable gate arrays (FPGAs)
that require separate core and I/O voltages.
Applications
• FPGA, CPLD, DSP, CPU core and I/O voltages
• Low-voltage, high-density distributed power systems
Related Literature
• AN1732 “ISL70002SEH 12A Synchronous Buck Regulator
Evaluation Board User Guide”
• AN1953 “ISL70002SEH Dual Phase Current Share
Evaluation Board User Guide”
Features
• DLA SMD 5962-12202
• Output current for a single device
- 14A at TJ = +125°C; 12A at TJ = +150°C
• Output current for two paralleled devices
- 22A at TJ = +125°C; 19A at TJ = +150°C
• Available in a thermally enhanced heatsink package - R64.C
• 1MHz or 500kHz switching frequency
• 3V to 5.5V supply voltage range
• ±1% Reference voltage (line, load, temp. and rad)
• Prebiased load compatible
• Redundancy/junction isolation: Exceptional SET
performance
• Excellent transient response
• High efficiency >90%
• Two ISL70002SEH synchronization, inverted-phase
• Comparator input for enable and power-good
• Input undervoltage, output undervoltage and adjustable
output overcurrent protection
• QML qualified per MIL-PRF-38535
• Full military temperature range operation (-55°C to +125°C)
• Radiation environment
- High dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)
- ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)*
*Level guaranteed by characterization; “EH” version is
production tested to 50krad(Si).
• SEE hardness
- SEL and SEB LETTH . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2
- SEFI LETTH. . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm2
- SET LETTH . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2
100
95
1.8V
2.5V
3.3V
90
85
80
75
1.2V
70
1.5V
65
1V
60
0 1 2 3 4 5 6 7 8 9 10 11 12
LOAD CURRENT (A)
FIGURE 1. EFFICIENCY 5V INPUT, 500kHz, Tcase = +25°C
25
20 CH1 MASTER LX + 20V
15
CH2 SLAVE LX + 15V
10
CH3 VOUT x 10
5
CH4 SYNC
0
-6 -4 -2 0 2 4 6 8 10 12 14
FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm2
October 1, 2015
FN8264.8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012-2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL70002SEH
Pin Descriptions (Continued)
R64.A
R64.C
PIN NUMBER PIN NUMBER PIN NAME
DESCRIPTION
14 ISHCOM ISHCOM is a bidirectional communication line between a current share master and a current share slave. If
using current share, tie ISHCOM of the master to ISHCOM of the slave. The master enables the slave by
resistively (~ 8.5kΩ) pulling ISHCOM high. The slave indicates an overcurrent fault condition to the master by
pulling ISHCOM low. To mitigate SET, connect a 47pF ceramic capacitor from ISHCOM to the PCB ground plane.
If not using current share this pin should be floated or connected to the PCB ground plane. ISHCOM is tri-stated
if ISHEN is low.
15 ISHSL This pin is a logic input that is used to configure the IC as a current share master or slave. Tie this pin to DVDD
to configure the IC as a current share slave. Tie this pin to the PCB ground plane to configure the IC as a current
share master, or if the current share feature is not being used.
16 ISHEN This pin is an input that enables/disables the current share feature. To enable the current share feature, tie
this pin to DVDD. To disable the current share feature, tie this pin to the PCB ground plane.
17 PORSEL This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For a nominal 5V
supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to DGND. For nominal supply
voltages between 5V and 3.3V, connect this pin to DGND.
18 TDO This pin is the test data output of the internal BIT circuitry. Connect this pin to the PCB ground plane.
19 TDI This pin is the test data input of the internal BIT circuitry. Connect this pin to the PCB ground plane.
20 TPGM This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to the PCB ground plane.
21 GND This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this
pin to the PCB ground plane.
22 SYNC When SYNC is configured as an output (clock Master Mode, M/S = DVDD), this pin drives the SYNC input of
another ISL70002SEH with a square ware that is inverted (~180° out-of-phase) from the master clockdriving
the master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the
SYNC output from another ISL70002SEH or an external clock to drive the clock slave PWM circuitry. If
synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the
range of 400kHz to 1.2MHz.
23, 28, 32, 37, 38, 43, 44,
49, 53, 58
PVINx
These pins are the power supply inputs to the corresponding internal power blocks. These pins must be
connected to a common power supply rail, which must fall in the range of 3V to 5.5V. Bypass these pins directly
to PGNDx with ceramic capacitors located as close as possible to the IC. PVINx should be the same voltage as
DVDD and AVDD (±200mV).
24, 27, 33, 36, 39, 42, 45,
48, 54, 57
LXx These pins are the outputs of the corresponding internal power blocks and should be connected to the output
filter inductor. Internally, these pins are connected to the synchronous MOSFET power switches.
25, 26, 34, 35, 40, 41, 46,
47, 55, 56
PGNDx
These pins are the power grounds associated with the corresponding internal power blocks. These pins also
provide the ground path for the metal package lid. Connect these pins directly to the PCB ground plane. These
pins should also connect to the negative terminals of the input and output capacitors. Locate the input and
output capacitors as close as possible to the IC.
29 M/S This pin is the clock master/slave input for selecting the direction of the bidirectional SYNC pin. For
SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to
the PCB ground plane.
30 FSEL This pin is the oscillator frequency select input. Tie this pin to DVDD to select a 1MHz nominal oscillator
frequency. Tie this pin to the PCB ground plane to select a 500kHz nominal oscillator frequency.
31, 50
31 NC, HS These are No Connect pins that are not connected to anything internally. They should be connected to the PCB
ground plane.
N/A 50 HS For the R64.C package (heatsink option) this pin is electrically connected to the heatsink on the underside of
the package. Connect this pin and/or the heatsink to a thermal plane.
Submit Document Feedback
5
FN8264.8
October 1, 2015
5 Page 
ISL70002SEH
Electrical Specifications Unless otherwise noted, VIN = AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 = 3V to 5.5V;
GND = AGND = DGND = PGNDx = ISHx = ISHCOM = ISHEN = ISHREFx = ISHSL = TDI = TDO = TPGM = 0V; FB = 0.65V; PORSEL = VIN for 4.5V ≤
VIN ≤ 5.5V and GND for VIN < 4.5V; LXx = SYNC = Open Circuit; OCx is connected to OCSSx with a 10kΩ resistor; OCx is connected to GND with a
4.99kΩ resistor shunted by a 6.8nF capacitor; PGOOD is pulled up to VIN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor;
SS is bypassed to GND with a 100nF capacitor; TA = TJ = -55°C to +125°C; Post 100krad(Si). (Note 9). (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
(Note 13) (Note 12) (Note 13)
UNITS
POWER-ON RESET
VIN POR
Rising threshold, PORSEL = VIN
Hysteresis, PORSEL = VIN
Rising threshold, PORSEL = GND
4.1
225
2.65
4.3
325
2.8
4.45
425
2.95
V
mV
V
Hysteresis, PORSEL = GND
70 140 240 mV
Enable (EN) Input Voltage
Rising/falling threshold
0.56
0.6
0.64
V
Enable (EN) Input Leakage Current
Enable (EN) Sink Current
VIN = 5.5V, EN = VIN or GND
EN = 0.3V
-3 3 µA
6.4
11
16.6
µA
SOFT-START
Soft-Start Source Current
SS = GND
20 23
27 µA
Soft-Start Discharge ON-Resistance
2.2 4.7 Ω
Soft-Start Discharge Time
256 Clock
Cycles
POWER-GOOD SIGNAL
Rising Threshold
Rising Hysteresis
Falling Threshold
Falling Hysteresis
Power-Good Drive
Power-Good Leakage
PROTECTION FEATURES
VFB as a % of VREF, test mode
VFB as a % of VREF, test mode
VFB as a % of VREF, test mode
VFB as a % of VREF, test mode
VIN = 3V, PGOOD = 0.4V, EN = GND
VIN = PGOOD = 5.5V
107 111
115
%
2 3.5 5 %
85 89 93 %
2 3.5 5 %
7.2 mA
1 µA
Undervoltage Monitor
Undervoltage Trip Threshold
Undervoltage Recovery Threshold
Overcurrent Monitor
VFB as a % of VREF, test mode
VFB as a % of VREF, test mode
71 75 79 %
84 88 92 %
Overcurrent Trip Level
CURENT SHARE
IOCx = 60µA, test mode (Note 17)
IOCx = 240µA, test mode (Note 17)
5.35
23
7.35 A
26 A
Slave Load Current
Master load current = 12A, VIN = 3.3V, VOUT = 0.8V,
7
12
17
A
SC1 = ISHSL = M/S = 0, SC0 = ISHEN = FSEL = 1,
SYNC = 1MHz external, 500nH inductor (Notes 15, 16)
Master load current = 12A, VIN = 3.3V, VOUT = 1.8V,
7
12
17
A
SC0 = ISHSL= M/S = 0, SC1 = ISHEN = FSEL = 1,
SYNC = 1MHz external, 500nH inductor (Notes 15, 16)
Master load current = 12A, VIN = 5.0V, VOUT = 1.8V,
7
12
17
A
SC0 = ISHSL = M/S = 0, SC1 = ISHEN = FSEL = 1,
SYNC = 1MHz external, 500nH inductor (Notes 15, 16)
Master load current = 12A, VIN = 5.0V, VOUT = 2.5V,
7
12
17
A
ISHSL = M/S = 0, SC0 = SC1 = ISHEN = FSEL = 1,
SYNC = 1MHz external, 500nH inductor (Notes 15, 16)
Submit Document Feedback 11
FN8264.8
October 1, 2015
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet ISL70002SEH.PDF ] | |
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