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PDF UT54ACS273E Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS273E | |
| Descripción | Octal D-Flip-Flops | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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UT54ACS273E
Octal D-Flip-Flops with Clear
March 2015
www.aeroflex.com/Logic
Datasheet
FEATURES
• Contains eight flip-flops with single-rail outputs
• Buffered clock and direct clear inputs
• Individual data input to each flip-flop
• Applications include:
- Buffer/storage registers, shift registers and pattern gener-
ators
• 0.6μm CRH CMOS process
- Latchup immune
• High speed
• Low power consumption
• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 20-lead flatpack
• UT54ACS273E - SMD 5962-96578
DESCRIPTION
The UT54ACS273E is a performance and voltage enhanced
version of the UT54ACS273 positive-edge-triggered D-type
flip-flop with a direct clear input.
Information at the D inputs meeting the setup time requirements
is transferred to the Q outputs on the positive-going edge of the
clock pulse. When the clock input is at either the high or low
level, the D input signal has no effect at the output.
The device is characterized over full HiRel temperature range
of -55°C to +125°C.
FUNCTION TABLE
INPUTS
OUTPUT
CLR
CLK
DX
QX
LXX
L
H↑H
H
H↑ L
L
H L X No Change
PINOUT
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VSS
20-Lead Flatpack
TopView
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VDD
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
LOGIC SYMBOL
CLR (1)
CLK (11)
R
C1
(3)
1D
2D (4)
3D (7)
4D (8)
5D (13)
6D (14)
7D (17)
8D (18)
1D
(2)
1Q
(5) 2Q
(6) 3Q
(9) 4Q
(12) 5Q
(15) 6Q
(16) 7Q
(19) 8Q
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
36-00-04-000
Ver. 1.0.0
1 Aeroflex Microelectronics Solutions - HiRel
1 page  
Ptotal2
Power dissipation 2, 8, 10
IDDQ Quiescent Supply Current
CIN Input capacitance 5
COUT Output capacitance 5
CL = 50pF
VDD = 3.0V to 3.6V
VIN = VDD or VSS
VDD from 3.0V to 5.5V
ƒ = 1MHz
VDD = 0V
ƒ = 1MHz
VDD = 0V
0.7 mW/
MHz
25 μA
15 pF
15 pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25°C per MIL-STD-883 method 1019 condition
A up to the maximum TID level procured.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
10. Power does not include power contribution of any TTL output sink current.
36-00-04-000
Ver. 1.0.0
5 Aeroflex Microelectronics Solutions - HiRel
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS273E.PDF ] | |
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