PDF UT54ACTS899 Data sheet ( Hoja de datos )

Número de pieza	UT54ACTS899
Descripción	9-bit Latchable Transceiver
Fabricantes	Aeroflex Circuit Technology
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No Preview Available ! Standard Products UT54ACTS899 9-bit Latchable Transceiver with Parity Generator/Checker Datasheet May 16, 2012 www.aeroflex.com/Logic FEATURES  Latchable transceiver with output source/sink of 24mA  Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A  Independent latch enable for A-to-B and B-to-A directions  Select pin for ODD/EVEN parity  ERRA and ERRB output pins for parity checking  Ability to simultaneously generate and check parity  m Commercial CMOS  Operational environment: - Total dose: 100K rad(Si) - Single Event Latchup immune - SEU immune  Standard Microcircuit Drawing 5962-06240 - QML compliant part  Package: - 28-pin ceramic flatpack DESCRIPTION The UT54ACTS899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The UT54ACTS899 features inde- pendent latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. PIN DESCRIPTION Inputs A0-A7 B0-B7 APAR, BPAR ODD/EVEN GBA, GAB SEL LEA, LEB ERRA, ERRB Outputs A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs ODD/EVEN Parity Select, Active LOW for EVEN Parity Output Enables for A or B Bus, Active Low Select Pin for Feed-through or Generate Mode, LOW for Generate Mode Latch Enables for A and B Latches, HIGH for Transparent Mode Error Signals for Checking Generated Par- ity with Parity In, LOW if Error Occurs 28-Lead Flatpack Pinout ODD/EVEN ERRA LEA A0 A1 A2 A3 A4 A5 A6 A7 APAR GBA VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD GAB B0 B1 B2 B3 B4 B5 B6 B7 BPAR LEB SEL ERRB 1 1 page DC ELECTRICAL CHARACTERISTICS* 1 ( VDD = 3.3 + 0.3V, TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER CONDITION MIN VIL Low level input voltage2 VIH High level input voltage2 IIN Input leakage current IOZ Three-state output leakage current IOS Short-circuit output current3, 4 VOL1 Low-level output voltage5 VOL2 Low-level output voltage5, 6 VOH1 High-level output voltage5 VOH2 High-level output voltage5, 6 VIC+ Positive input clamp voltage VIC- Negative input clamp voltage VDD from 4.5V to 5.5V VDD from 4.5V to 5.5V 2.0 VDD from 4.5 to 5.5 VIN = VDD or VSS -1 VDD from 4.5 to 5.5 VIN = VDD or VSS -10 VO = VDD or VSS VDD from 4.5 to 5.5 -600 IOL= 24mA -55C, +25oC IOL= 24mA +125oC IOL= 100A VIN = 2.0V or 0.8V VDD = 4.5 to 5.5 IOL= 50mA -55C, +25oC VIN = 2.0V or 0.8V VDD = 5.5V +125oC IOH= -24mA -55, +25oC IOH= -24mA +125oC IOH= -100A VIN = 2.0V or 0.8V VDD = 4.5 to 5.5V VDD - 0.64 VDD - 0.8 VDD - 0.2 IOH= -50mA VIN = 2.0V or 0.8V VDD = 5.5V -55C, 25oC +125oC VDD -1.1 VDD -1.25 For input under test, IIN = +18mA VDD = 0.0V 0.4 For input under test, IIN = -18mA VDD = open -1.5 MAX 0.8 1 10 600 0.4 0.5 0.2 0.8 1.0 1.5 -0.4 UNIT V V A A mA V V V V V V 5 5 Page An (Bn) EVEN PARITY ODD/EVEN VIM VIM BPAR (APAR) Note: 1. VIM = 1.5V, VOM = VDD/2 2. SEL = APAR (BPAR) = VSS = L tPLH6 VOM tPHL6 VOM +3.0V INPUT 0V +3.0V INPUT 0V VOH VOM OUTPUT VOL Figure 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR (with Even Parity Mode Shown) An (Bn) APAR (BPAR) ERRA (ERRB) Note: 1. VIM = 1.5V, VOM = VDD/2 2. ODD/EVEN = VSS = L EVEN PARITY VIM VIM tPLH7 VOM tPHL7 VOM +3.0V INPUT 0V +3.0V INPUT 0V VOH VOM OUTPUT VOL Figure 6. Propagation Delay, APAR to ERRA or BPAR to ERRB (With Even Parity Mode Shown with Even Data Parity. Odd Parity Mode would cause Inverted Output.) 11 11 Page

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