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PDF UT8Q512K32E Data sheet ( Hoja de datos )
| Número de pieza | UT8Q512K32E | |
| Descripción | 16 Megabit RadTolerant SRAM MCM | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT8Q512K32E 16 Megabit RadTolerant SRAM MCM
Data Sheet
June 28, 2011
FEATURES
25ns maximum (3.3 volt supply) address access time
MCM contains four (4) 512Kx8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24 or 32-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- SEL Immune >110 MeV-cm2/mg
- SEU LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section , 2.8E-8 cm2/bit
- <1.1E-9 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
INTRODUCTION
The UT8Q512K32E RadTolerant product is a high-performance
2M byte (16Mbit) CMOS static RAM multi-chip module
(MCM), organized as four individual 524,288 x 8 bit SRAMs
with a common output enable. Memory expansion is provided
by an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power-
down feature that reduces power consumption by more than 90%
when deselected.
Writing to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
Standard Microcircuit Drawing 5962-01533
- QML Q and Vcompliant part
W3
E3
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT8Q512K32E SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
1
1 page  
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-40C to +105C (VDD = 3.3V + 0.3V)
SYMBOL
PARAMETER
CONDITION
MIN MAX UNIT
VIH High-level input voltage
(TTL)
2.0
VIL
VOL1
Low-level input voltage
Low-level output voltage
(TTL)
IOL = 6mA, VDD = 3.0V (TTL)
0.8
0.4
VOL2 Low-level output voltage
IOL = 200A,VDD = 3.0V (CMOS)
0.08
VOH1 High-level output voltage
IOH = -4mA,VDD = 3.0V (TTL)
2.4
VOH2 High-level output voltage
IOH = 200A,VDD = 3.0V (CMOS)
VDD -.010
CIN1 Input capacitance
= 1MHz @ 0V
45
CIO1 Bidirectional I/O capacitance
= 1MHz @ 0V
25
IIN Input leakage current
VIN = VDD and VSS, VDD = VDD (max)
-2 2
IOZ Three-state output leakage current VO = VDD and VSS
VDD = VDD (max)
G = VDD (max)
-2 2
IOS2, 3 Short-circuit output current
VDD = VDD (max), VO = VDD
VDD = VDD (max), VO = 0V
-90 90
IDD(OP)
Supply current operating
@ 1MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
40
IDD1(OP) Supply current operating
@40MHz
(per byte)
Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
70
IDD2(SB)4 Supply current standby
@0MHz
(per byte)
Inputs: VIL = VSS
IOUT = 0mA
E1 = VDD - 0.5, VDD =
VDD (max)
VIH = VDD - 0.5V
-40C &
25C
105C
9
24
V
V
V
V
V
V
pF
pF
A
A
mA
mA
mA
mA
mA
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Post-radiation limit based off of high temperature limit.
5
5 Page 
VDD
EN
DATA RETENTION MODE
3.0V
VDR > 2.0V
tEFR
3.0V
tR
VDD = VDR
Figure 7. Low VDD Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre-Radiation) *(VDD2 = VDD2 (min), 1 Sec DR Pulse)
SYMBOL
PARAMETER
TEMP
MINIMUM MAXIMUM
VDR
IDDR 1
tEFR1
tR1
VDD1 for data retention
Data retention current
(per byte)
Chip deselect to data retention time
Operation recovery time
--
-40oC & 25oC
105oC
--
--
2.0
--
0
tAVAV
--
9
24
--
--
Notes:
*Post-radiation performance guaranteed at 25oC per MIL-STD-883 Method 1019.
1. E n= VDR all other inputs = VDR or VSS
UNIT
V
mA
mA
ns
ns
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet UT8Q512K32E.PDF ] | |
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