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PDF MX30LF1G18AC Data sheet ( Hoja de datos )
| Número de pieza | MX30LF1G18AC | |
| Descripción | 1G-bit NAND Flash Memory | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX30LF1G18AC
3V, 1G-bit NAND Flash Memory
MX30LF1G18AC
P/N: PM2133
REV. 1.2, May 27, 2016
1
1 page  
1. FEATURES
• 1G-bit SLC NAND Flash
- Bus: x8
- Page size: (2048+64) byte,
- Block size: (128K+4K) byte,
• ONFI 1.0 compliant
• Multiplexed Command/Address/Data
• User Redundancy
- 64-byte attached to each page
• Fast Read Access
- Latency of array to register: 25us
- Sequential read: 20ns
• Cache Read Support
• Page Program Operation
- Page program time: 300us( typ.)
• Cache Program Support
• Block Erase Operation
- Block erase time: 1ms (typ.)
• Single Voltage Operation:
- VCC: 2.7 - 3.6V
• Low Power Dissipation
- Max. 30mA
Active current (Read/Program/Erase)
• Sleep Mode
- 50uA (Max) standby current
• Hardware Data Protection: WP# pin
MX30LF1G18AC
3V, 1Gb NAND Flash Memory
• Block Protection
- PT (Protection) pin: active high at power-on,
which protects the entire chip. The pin has an
internal weak pull down.
- Temporary protection/un-protection function
(enabling by PT pin)
- Solid protection
(enabling by PT pin)
• Device Status Indicators
- Ready/Busy (R/B#) pin
- Status Register
• Chip Enable Don't Care
- Simplify System Interface
• Unique ID Read support (ONFI)
• Secure OTP support
• High Reliability
- Endurance: typical 100K cycles (with 4-bit ECC
per (512+16) Byte)
- Data Retention: 10 years
• Wide Temperature Operating Range
-40°C to +85°C
• Package:
1) 48-TSOP(I) (12mm x 20mm)
2) 63-ball 9mmx11mm VFBGA
All packaged devices are RoHS Compliant and
Halogen-free.
P/N: PM2133
REV. 1.2, May 27, 2016
5
5 Page 
MX30LF1G18AC
PIN FUNCTIONS
The MX30LF1G18AC device is a sequential
access memory that utilizes multiplexing input of
Command/Address/Data.
I/O PORT: IO7 - IO0
The IO7 to IO0 pins are for address/command
input and data output to/from the device.
CHIP ENABLE: CE#
The device goes into low-power Standby Mode
when CE# goes high during a read operation and
not at busy stage.
The CE# goes low to enable the device to be
ready for standard operation. When the CE# goes
high, the device is deselected. However, when the
device is at busy stage, the device will not go to
standby mode when CE# pin goes high.
READ ENABLE: RE#
The RE# (Read Enable) allows the data to be
output by a tREA time after the falling edge of
RE#. The internal address counter is automatically
increased by one at the falling edge of RE#.
WRITE ENABLE: WE#
When the WE# goes low, the address/data/
command are latched at the rising edge of WE#.
COMMAND LATCH ENABLE: CLE
The CLE controls the command input. When the
CLE goes high, the command data is latched at the
rising edge of the WE#.
ADDRESS LATCH ENABLE: ALE
The ALE controls the address input. When the ALE
goes high, the address is latched at the rising edge
of WE#.
WRITE PROTECT: WP#
The WP# signal keeps low and then the memory will
not accept the program/erase operation. It is recom-
mended to keep WP# pin low during power on/off
sequence. Please refer to Figure 37. Power On/Off
Sequence.
READY/Busy: R/B#
The R/B# is an open-drain output pin. The R/B#
outputs the ready/busy status of read/program/
erase operation of the device. When the R/B# is at
low, the device is busy for read or program or erase
operation. When the R/B# is at high, the read/
program/erase operation is finished.
Please refer to 8-1. R/B#: Termination for The
Ready/Busy# Pin (R/B#) for details.
PT: Protection
When the PT pin is high at power on, the whole
chip is protected even the WP# is at high; the un-
protection procedure (through BP bits setting) is
necessary before any program/erase operation.
When the PT pin is connected to low or floating, the
function of block protection is disabled.
P/N: PM2133
REV. 1.2, May 27, 2016
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MX30LF1G18AC.PDF ] | |
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