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PDF IP4788CZ32 Data sheet ( Hoja de datos )

Número de pieza IP4788CZ32
Descripción DVI and HDMI interface ESD and overcurrent protection
Fabricantes NXP Semiconductors　
Logotipo NXP Semiconductors Logotipo



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IP4788CZ32
DVI and HDMI interface ESD and overcurrent protection,
DDC/CEC buffering, hot plug detect and backdrive protection
Rev. 2 — 24 November 2014
Product data sheet
1. Product profile
1.1 General description
The IP4788CZ32 is designed to protect High-Definition Multimedia Interface (HDMI)
transmitter host interfaces. It includes HDMI 5 V overcurrent / overvoltage protection,
Display Data Channel (DDC) buffering and decoupling, hot plug detect, backdrive
protection, Consumer Electronic Control (CEC) buffering and decoupling, and 14 kV
contact ElectroStatic Discharge (ESD) protection for all external I/Os, far exceeding the
IEC 61000-4-2, level 4 standard.
The IP4788CZ32 incorporates Transmission Line Clamping (TLC) technology on the
high-speed Transition Minimized Differential Signaling (TMDS) lines to simplify routing
and help reducing impedance discontinuities. All TMDS lines are protected by an
impedance-matched diode configuration that minimizes impedance discontinuities caused
by typical shunt diodes.
The enhanced 60 mA overcurrent / overvoltage linear regulator guarantees
HDMI-compliant 5 V output voltage levels with up to 6.5 V inputs.
The DDC lines use a new buffering concept which decouples the internal capacitive load
from the external capacitive load for use with standard Complementary Metal Oxide
Semiconductor (CMOS) or Low Voltage Transistor-Transistor Logic (LVTTL) I/O cells
down to 1.8 V. This buffering also redrives the DDC and CEC signals, allowing the use of
longer or cheaper HDMI cables with a higher capacitance. The internal hot plug detect
module simplifies the application of the HDMI transmitter to control the hot plug signal.
All lines provide appropriate integrated pull-ups and pull-downs for HDMI compliance and
backdrive protection to guarantee that HDMI interface signals are not pulled down when
the system is powered down or enters Standby mode. Only a single external capacitor is
required for operation.
1.2 Features and benefits
HDMI 2.0 and all backward compatible standards are supported
6.0 Gbps TMDS Bit Rate (600 Mcsc TMDS Character Rate) compatible
Supports Ultra High-Definition (UHD) 4K (2160p) 60 Hz display modes
Impedance matched 100 differential transmission line ESD protection for
TMDS lines (10 ). No Printed-Circuit Board (PCB) pre-compensation required
Simplified flow-through routing utilizing less overall PCB space
DDC capacitive decoupling between system side and HDMI connector side and
buffering to drive cable with high capacitive load (> 700 pF/25 m)

1 page




IP4788CZ32 pdf
NXP Semiconductors
4. Functional diagram
IP4788CZ32
DVI and HDMI interface ESD and overcurrent protection
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IP4788CZ32
IP4788CZ32
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 33

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IP4788CZ32 arduino
NXP Semiconductors
IP4788CZ32
DVI and HDMI interface ESD and overcurrent protection
Table 8. Static characteristics …continued
Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
HOTPLUG_DET_SYS[1]
VOH HIGH-level output voltage IOL = 1 mA
VOL LOW-level output voltage IOL = 1 mA
Rpd pull-down resistance
Min Typ
0.7 VCC(SYS)
-
60
-
200
100
[1] The device is active if the input voltage at pin CEC_STBY is above the HIGH level.
[2] This parameter is guaranteed by design.
[3] Capacitive load measured at power-on.
[4] No external pull-up resistor attached.
Max
-
300
140
Unit
V
mV
k
Table 9. CEC_STBY power management circuit
VCC(SYS) = 1.62 V to 5.5 V; VCC(5V0) = 4.5 V to 6.5 V; GND = 0 V; Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
Board side: input pin CEC_STBY[1]
VIH
HIGH-level input voltage
HIGH = active
[2] 1.2
-
6.5 V
VIL
LOW-level input voltage
LOW = standby
[3] 0.5
-
0.8 V
Rpd pull-down resistance
60 100 140 k
Ci input capacitance
VI = 3 V or 0 V
- 6 7 pF
[1] The CEC_STBY pin should be connected permanently to VCC(5V0) or VCC(SYS) if no enable control is needed.
[2] DDC buffers, Hot Plug Detect (HPD) buffer, and HDMI_5V0_CON out enabled; CEC buffer enabled.
[3] DDC buffers, HPD buffer, and HDMI_5V0_CON out disabled; CEC buffer enabled.
7. Dynamic characteristics
Table 10. Dynamic characteristics
VCC(5V0) = 5.0 V; VCC(SYS) = 1.8 V; GND = 0 V; Tamb = 25 C to +85 C unless otherwise specified.
Symbol Parameter
Conditions
Min
DDC_DAT_SYS, DDC_CLK_SYS, DDC_DAT_CON, DDC_CLK_CON[1]
tPLH LOW to HIGH propagation delay system side to connector side Figure 11 -
tPHL HIGH to LOW propagation delay system side to connector side Figure 11 -
tPLH LOW to HIGH propagation delay connector side to system side Figure 12 -
tPHL HIGH to LOW propagation delay connector side to system side Figure 12 -
tTLH
LOW to HIGH transition time
connector side Figure 13
tTHL
HIGH to LOW transition time
connector side Figure 13
-
-
tTLH
LOW to HIGH transition time
system side Figure 14
-
tTHL
HIGH to LOW transition time
system side Figure 14
-
Typ
80
60
120
80
150
100
250
80
[1] All dynamic measurements are done with a 75 pF load. Rise times are determined by internal pull-up resistors.
Max Unit
- ns
- ns
- ns
- ns
- ns
- ns
- ns
- ns
IP4788CZ32
IP4788CZ32
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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