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PDF LCM1602A-FSYG-GBW Data sheet ( Hoja de datos )
| Número de pieza | LCM1602A-FSYG-GBW | |
| Descripción | LCD MODULE | |
| Fabricantes | LONGTECH OPTICS | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LCM1602A-FSYG-GBW (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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LONGTECH
OPTICS
Address: 5F No. 88 Sunban South Road
Jimei North Area Xiamen China.
SPECIFICATIONS OF
LCD MODULE
MODULE NO : LCM1602A-FSYG-GBW
DOC.REVISION: 00
PREPARED BY
(RD ENGINEER)
CHECKED BY
APPROVED BY
SIGNATURE
QIU
DATE
2011-1-7
2011-1-7
2011-1-7
1 page  
4. Absolute maximum ratings
Item
Symbol
Power voltage
VDD-VSS
Input voltage
Operating temperature range
Storage temperature range
VIN
VOP
VST
5. Block diagram
0
VSS
-20
-30
Standard
-
-
-
-
7.0
VDD
70
80
Unit
V
℃
6. Interface pin description
Pin no.
1
2
3
4
5
6
7~10
Symbol
Vss
VDD
V0
RS
R/W
E
DB0~DB3
11~14
15
16
DB4~DB7
LED+
LED-
External
connection
Power supply
MPU
MPU
MPU
MPU
MPU
LED BKL power
supply
Function
Signal ground for LCM
Power supply for logic for LCM
Contrast adjust
Register select signal
Read/write select signal
Operation (data read/write) enable signal
Four low order bi-directional three-state data bus lines.
Used for data transfer between the MPU and the LCM.
These four are not used during 4-bit operation.
Four high order bi-directional three-state data bus lines.
Used for data transfer between the MPU
Power supply for BKL
Power supply for BKL
5 Page 
LCM1602A-FSYG-GBW
LONGTECH OPTICS
9) Read busy flag & address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
This instruction shows whether SPLC780D is in internal operation or not.
If the resultant BF is “High”, internal operation is in progress and should wait BF is to be LOW, which by then
the nest instruction can be performed. In this instruction you can also read the value of the address counter.
10) Write data to RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM
address set, CGRAM address set).
RAM set instruction can also determine the AC direction to RAM.
After write operation. The address is automatically increased/decreased by 1, according to the entry mode.
11) Read data from RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM
is not performed before this instruction, the data that has been read first is invalid, as the direction of AC is not
yet determined. If RAM data is read several times without RAM address instructions set before, read operation,
the correct RAM data can be obtained from the second. But the first data would be incorrect, as there is no
time margin to transfer RAM data.
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set
instruction, it also transfers RAM data to output data register.
After read operation, address counter is automatically increased/decreased by 1 according to the entry
mode.
After CGRAM read operation, display shift may not be executed correctly.
NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation.
At this time, AC indicates next address position, but only the previous data can be read by the read
instruction.
12.Display character address code:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
11 / 20
11 Page | ||
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| PDF Descargar | [ Datasheet LCM1602A-FSYG-GBW.PDF ] | |
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