PDF GS8662S36BGD Data sheet ( Hoja de datos )

Número de pieza	GS8662S36BGD
Descripción	72Mb SigmaSIO DDR -II Burst of 2 SRAM
Fabricantes	GSI Technology
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GS8662S08/09/18/36BD-400/350/333/300/250 165-Bump BGA Commercial Temp Industrial Temp 72Mb SigmaSIOTM DDR -II Burst of 2 SRAM 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available SigmaSIO™ Family Overview GS8662S08/09/18/36BD are built in compliance with the SigmaSIO DDR-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaSIO DDR-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO DDR-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination. Each internal read and write operation in a SigmaSIO DDR-II B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate incoming data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a SigmaSIO DDR-II B2 is always one address pin less than the advertised index depth (e.g., the 8M x 8 has an 4M addressable index). Parameter Synopsis tKHKH tKHQV -400 2.5 ns 0.45 ns -350 2.86 ns 0.45 ns -333 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns Rev: 1.02c 12/2011 1/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology 1 page GS8662S08/09/18/36BD-400/350/333/300/250 2M x 36 SigmaQuad SRAM—Top View 1 2 3 4 5 6 7 8 9 10 A CQ NC/SA (288Mb) SA R/W BW2 K BW1 LD SA NC/SA (144Mb) B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17 C D27 Q28 D19 VSS SA SA SA VSS D16 Q7 D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 E Q29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 F Q30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 G D30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 H DOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF J D31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 K Q32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 L Q33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 N D34 D26 Q25 VSS SA SA SA VSS Q10 D9 P Q35 D35 Q26 SA SA C SA SA Q9 D0 R TDO TCK SA SA SA C SA SA SA TMS 11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch Notes: 1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17. 2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35. 3. A2 and A10 are the expansion addresses. 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Rev: 1.02c 12/2011 5/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2011, GSI Technology 5 Page GS8662S08/09/18/36BD-400/350/333/300/250 FLXDrive-II Output Driver Impedance Control HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table A LD R/W Current Operation DD K↑ K↑ K↑ (tn) (tn) (tn) K↑ (tn) K↑ (tn + 1) K↑ (tn + 1½) X1X Deselect XX V01 Read XX V00 Write D0 D1 Notes: 1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care” 2. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations. 3. D0 and D1 indicate the first and second pieces of input data transferred during Write operations. 4. Users should not clock in metastable addresses. Q K↑ (tn + 1½) Hi-Z Q0 Hi-Z Q K↑ (tn + 2) Hi-Z Q1 Hi-Z Burst of 2 Byte Write Clock Truth Table BW BW Current Operation K↑ (tn + 1) K↑ (tn + 1½) K↑ (tn) TT Write Dx stored if BWn = 0 in both data transfers TF Write Dx stored if BWn = 0 in 1st data transfer only FT Write Dx stored if BWn = 0 in 2nd data transfer only FF Write Abort No Dx stored in either data transfer Notes: 1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”. 2. If one or more BWn = 0, then BW = “T”, else BW = “F”. Rev: 1.02c 12/2011 11/35 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D K↑ (tn + 1) D1 D1 X X D K↑ (tn + 1½) D2 X D2 X © 2011, GSI Technology 11 Page

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