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GSI Technology - 72Mb SigmaDDR-II+ Burst of 2 ECCRAM

Numéro de référence GS8672T38BGE
Description 72Mb SigmaDDR-II+ Burst of 2 ECCRAM
Fabricant GSI Technology 
Logo GSI Technology 





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GS8672T38BGE fiche technique
GS8672T20/38BE-633/550/500/450/400
165-Bump BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-II+TM
Burst of 2 ECCRAMTM
633 MHz–400 MHz
1.8 V VDD
1.5 V I/O
Features
• 2.5 Clock Latency
• On-Chip ECC with virtually zero SER
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard package
• Double Data Rate interface
• Byte Write capability
• Burst of 2 Read and Write
• On-Die Termination (ODT) on Data (DQ), Byte Write (BW),
and Clock (K, K) outputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with 36Mb and 144Mb devices
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDRECCRAM Overview
The GS8672T20/38BE SigmaDDR-II+ ECCRAMs are built in
compliance with the SigmaDDR-II+ SRAM pinout standard
for Common I/O synchronous SRAMs. They are
75,497,472-bit (72Mb) SRAMs. The GS8672T20/38BE
SigmaDDR SRAMs are just one element in a family of low
power, low voltage HSTL I/O SRAMs designed to operate at
the speeds needed to implement economical high performance
networking systems.
Clocking and Addressing Schemes
The GS8672T20/38BE SigmaDDR-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaDDR-II+ B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaDDR-II+ B2 ECCRAM is always one address
pin less than the advertised index depth (e.g., the 4M x 18 has
an 2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
However, the On-Chip Error Correction (ECC) will be
disabled if a “Half Write” operation is initiated. See the Byte
Write Contol section for further information.
tKHKH
tKHQV
-633
1.57 ns
0.45 ns
Parameter Synopsis
-550
1.81 ns
0.45 ns
-500
2.0 ns
0.45 ns
-450
2.2 ns
0.45 ns
-400
2.5 ns
0.45 ns
Rev: 1.02a 6/2013
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology

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