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PDF M25PE20 Data sheet ( Hoja de datos )
| Número de pieza | M25PE20 | |
| Descripción | 2Mb and 1Mb 3V NOR Serial Flash Memory | |
| Fabricantes | Micron | |
| Logotipo |  |
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M25PE20, M25PE10 Serial Flash Embedded Memory
Features
M25PE20/M25PE10 2Mb and 1Mb
3V NOR Serial Flash Memory
Serial Flash Memory with Byte Alterability, 75 MHz SPI bus, Standard
Pinout
Features
• 1Mb or 2Mb of page-erasable Flash memory
• 2.7V to 3.6V single supply voltage
• SPI bus compatible serial interface
• 75 MHz clock rate (maximum)
• Page size: 256 bytes
– Page write in 11ms (TYP)
– Page program in 0.8ms (TYP)
– Page erase in 10ms (TYP)
• Subsector erase: 32Kb
– Sector erase: 512Kb
– Bulk erase: 1Mb for M25PE10; 2Mb for M25PE20
• Deep power-down mode: 1µA (TYP)
• Electronic signature
– JEDEC standard 2-byte signature (8012h for
M25PE20; 8011h for M25PE10)
• Software write-protection on a 64KB sector basis
• More than 100,000 write cycles per sector
• More than 20 years of data retention
• Hardware write protection of the memory area se-
lected using the BP0 and BP1 bits
• Packages (RoHS compliant)
– SO8N (MN) 150 mil width
– VFQFPN8 (MP) 6mm x 5mm
• Automotive grade parts available
PDF: 09005aef845660ef
m25pe20_10.pdf - Rev. C 3/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1 page  
M25PE20, M25PE10 Serial Flash Embedded Memory
Functional Description
Functional Description
The M25PE20 and M25PE10 are 2Mb (256Kb x 8 bit) and 1Mb (128Kb x 8 bit) serial-pag-
ed Flash memory devices, respectively, accessed by a high-speed SPI-compatible bus.
The memories can be written or programmed 1 to 256 bytes at a time using the PAGE
WRITE or PAGE PROGRAM command. The PAGE WRITE command consists of an inte-
grated PAGE ERASE cycle followed by a PAGE PROGRAM cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages. Each page
is 256 bytes wide. The entire memory can be viewed as consisting of 1024 pages, or
262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages. Each page
is 256 bytes wide. The entire memory can be viewed as consisting of 512 pages, or
131,072 bytes.
The memories can be erased one page at a time using the PAGE ERASE command, one
sector at a time using the SECTOR ERASE command, one subsector at a time using the
SUBSECTOR ERASE command, or as a whoe using the BULK ERASE command.
The memories can be write-protected by either hardware or software using a mix of vol-
atile and non-volatile protection features, depending on application needs. The protec-
tion granularity is 64KB (sector granularity). The entire memory array is partitioned into
4KB subsectors.
Figure 1: Logic Diagram
VCC
DQ0
C
S#
W#
RESET#
DQ1
VSS
PDF: 09005aef845660ef
m25pe20_10.pdf - Rev. C 3/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
5 Page 
M25PE20, M25PE10 Serial Flash Embedded Memory
Operating Features
For optimized timings, it is recommended to use the PAGE PROGRAM (PP) instruction
to program all consecutive targeted bytes in a single sequence versus using several
PAGE PROGRAM (PP) sequences with each containing only a few bytes.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (tPW, tPP, tPE, tBE, tWor tSE).
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Reset
An internal power-on reset circuit helps protect against inadvertent data writes. Addi-
tional protection is provided by driving RESET# LOW during the power-on process, and
only driving it HIGH when VCC has reached the correct voltage level, VCC(min).
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected and in the ACTIVE POWER mode.
When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER
mode until all internal cycles have completed (PROGRAM, ERASE, WRITE). The device
then goes in to the STANDBY POWER mode. The device consumption drops to ICC1.
The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command
is executed. The device consumption drops further to ICC2. The device remains in this
mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in
the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations.
Status Register
The status register contains a number of status bits that can be read by the READ STA-
TUS REGISTER (RDSR) command.
Protection Modes
Non-volatile memory is used in environments that can include excessive noise. The fol-
lowing capabilities help protect data in these noisy environments.
Power on reset and an internal timer (tPUW) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
WRITE, PROGRAM, and ERASE commands are checked before they are accepted for ex-
ecution to ensure they consist of a number of clock pulses that is a multiple of eight.
All commands that modify data must be preceded by a WRITE ENABLE command to set
the write enable latch (WEL) bit. This bit is returned to its reset state by the following
events.
• Power-up
• Reset (RESET#) driven LOW
PDF: 09005aef845660ef
m25pe20_10.pdf - Rev. C 3/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2013 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet M25PE20.PDF ] | |
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