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PDF LPC4367JET100 Data sheet ( Hoja de datos )
| Número de pieza | LPC4367JET100 | |
| Descripción | 32-bit ARM Cortex-M4/M0 MCU | |
| Fabricantes | NXP Semiconductors | |
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LPC436x
32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 154 kB
SRAM; Ethernet, two High-speed USB, LCD, EMC
Rev. 1.2 — 14 March 2016
Product data sheet
1. General description
The LPC436x are ARM Cortex-M4 based microcontrollers for embedded applications,
which include an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for
managing peripherals, up to 1 MB of flash and 154 kB of on-chip SRAM, 16 kB of
EEPROM memory, a quad SPI Flash Interface (SPIFI), advanced configurable
peripherals such as the SCTimer/PWM and the Serial General Purpose I/O (SGPIO)
interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller,
and multiple digital and analog peripherals. The LPC436x operate at CPU frequencies of
up to 204 MHz.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A
hardware floating-point processor is integrated into the core.
The LPC436x include an application ARM Cortex-M0 coprocessor and a second ARM
Cortex-M0 subsystem for managing the SGPIO and SPI peripherals.The ARM Cortex-M0
coprocessor is an energy-efficient and easy-to-use 32-bit core which is upward code- and
tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor, designed as a
replacement for existing 8/16-bit microcontrollers, offers up to 204 MHz performance with
a simple instruction set and reduced code size. In LPC436x, the Cortex-M0 coprocessor
hardware multiply is implemented as a 32-cycle iterative multiplier.
For additional documentation related to the LPC43xx parts, see Section 17.
2. Features and benefits
Cortex-M4 Processor core
ARM Cortex-M4 processor (version r0p1), running at frequencies of up to
204 MHz.
Built-in Memory Protection Unit (MPU) supporting eight regions.
Built-in Nested Vectored Interrupt Controller (NVIC).
Hardware floating-point unit.
Non-maskable Interrupt (NMI) input.
JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch
points.
Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.
1 page  
NXP Semiconductors
LPC436x
32-bit ARM Cortex-M4/M0 microcontroller
4. Ordering information
Table 1. Ordering information
Type number
Package
Name
Description
LPC4367JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17 17 1 mm
LPC4367JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm
LPC4367JET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm
Version
SOT740-2
SOT459-1
SOT926-1
4.1 Ordering options
Table 2. Ordering options
LPC4367JET256 1 MB 512 kB 512 kB 154 kB yes yes yes yes/yes yes yes 8 J
LPC4367JBD208 1 MB 512 kB 512 kB 154 kB yes yes yes yes/yes yes yes 8 J
LPC4367JET100 1 MB 512 kB 512 kB 154 kB no yes yes yes/no yes yes 4 J
[1] J = -40 °C to +105 °C; F = -40 °C to +85 °C.
164
142
49
LPC436X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 156
5 Page 
NXP Semiconductors
Table 3. Pin description …continued
Pin name
LPC436x
32-bit ARM Cortex-M4/M0 microcontroller
Description
P1_5
P1_6
P1_7
R5
J4 65
[2] N; I/O GPIO1[8] — General purpose digital input/output pin.
PU O CTOUT_10 — SCT output 10. Match output 3 of timer 3.
- R — Function reserved.
O EMC_CS0 — LOW active Chip Select 0 signal.
I USB0_PWR_FAULT — Port power fault signal indicating
overcurrent condition; this signal monitors over-current on the
USB bus (external circuitry required to detect over-current
condition).
I/O SSP1_SSEL — Slave Select for SSP1.
I/O SGPIO15 — General purpose digital input/output pin.
O SD_POW — SD/MMC power monitor output.
T4
K4 67
[2] N; I/O GPIO1[9] — General purpose digital input/output pin.
PU I CTIN_5 — SCT input 5. Capture input 2 of timer 2.
- R — Function reserved.
O EMC_WE — LOW active Write Enable signal.
- R — Function reserved.
O EMC_BLS0 — LOW active Byte Lane select signal 0.
I/O SGPIO14 — General purpose digital input/output pin.
I/O SD_CMD — SD/MMC command signal.
T5
G4 69
[2] N; I/O GPIO1[0] — General purpose digital input/output pin.
PU I U1_DSR — Data Set Ready input for UART1.
O CTOUT_13 — SCT output 13. Match output 3 of timer 3.
I/O EMC_D0 — External memory data line 0.
O USB0_PPWR — VBUS drive signal (towards external charge
pump or power management unit); indicates that VBUS must
be driven (active HIGH).
Add a pull-down resistor to disable the power switch at reset.
This signal has opposite polarity compared to the USB_PPWR
used on other NXP LPC parts.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
LPC436X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 14 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 156
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