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PDF LV5239TA Data sheet ( Hoja de datos )
| Número de pieza | LV5239TA | |
| Descripción | 24-channel LED Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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LV5239TA
Bi-CMOS LSI
24-channel LED Driver
Overview
The LV5239TA is a 24-channel LED driver IC that is capable of switching
between constant-current output and open drain output. It enables
2-wire/3-wire serial bus control (address designation) to be set arbitrarily
using an external pin. Also possible are 24-channel LED ON/OFF control
and the setting of the PWM luminance in 256 steps.
Up to 32 driver ICs can be connected using the slave address setting pins.
www.onsemi.com
TQFP48 EP 7x7, 0.5P
Function
24-channel output constant-current LED driver/open drain output LED driver (selected by using an external pin).
Supports separate ON/OFF setting for each LED output, high withstand voltage (VOUT<42V).
In the constant-current mode (OUTSCT: L), the reference current is set by the value of resistor connected to the
external pin (RT1).
Built-in D/A (3 bits) for switching current level … 6.40mA to 32.40mA (RGB drive).
Constant current (IO max=50mA) for full-color LEDs 24 channels.
In the open drain mode (OUTSCT: H), high current drive
(IO max=100mA) 24 channels
In the constant-current mode (OUTSCT: M)
Only RGB7, RGB8 is open drain (IO max=100mA)
Luminance adjustment using internal PWM control (256 steps), It copes with independent PWM control for each
LED output.
8-bit PWM luminance dimming (0% to 99.6%)
8-phase PWM
Selection of 2-wire/ 3-wire serial bus control signals enabled (switching using an external pin).
Schmitt trigger input (3.3V/5V)
Slave addressing (5 bits, connection of up to 32 driver ICs possible)
Input Power supply supports 12V
Internal reference output terminal (5V)
Low current consumption
Output malfunction protection circuits
(thermal protection function, UVLO detection protection function, Power on RESET)
ORDERING INFORMATION
See detailed ordering and shipping information on page 28 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
February 2016 - Rev. 0
1
Publication Order Number :
LV5239TA/D
1 page  
Package Dimensions
unit : mm
LV5239TA
TQFP48 EP 7x7, 0.5P
CASE 932F
ISSUE C
37
NOTE 7
A
NOTES
4 & 6 E1
NOTE 9
D
NOTE 7
D
25
4X 12 TIPS
0.20 C A-B D
NOTE 7
B
NOTE 9
E
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL BE 0.08 MAX. AT MMC. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OF THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD IS 0.07.
SIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.25 PER SIDE. DIMENSIONS D1 AND E1
ARE MAXIMUM PLASTIC BODY SIZE INCLUDING MOLD MISMATCH.
5. THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE SIZE BY AS MUCH AS 0.15.
6. DATUMS A-B AND D ARE DETERMINED AT DATUM PLANE H.
7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM THE SEATING
8. DIMENSIONS D AND E TO BE DETERMINED AT DATUM PLANE C.
48 13
0.08 C
1
D1
NOTES 4 & 6
TOP VIEW
DETAIL A
4X
0.20 H A-B D
H
A A2
0.05
e
48X b
C
SEATING
PLANE
0.20 C A-B D
SIDE VIEW
NOTE 3
A1 L
DETAIL A
MILLIMETERS
DIM MIN MAX
A 0.95 1.25
A1 0.05 0.15
A2 0.90 1.20
b 0.17 0.27
D 9.00 BSC
D1 7.00 BSC
D2 4.90 5.10
E 9.00 BSC
E1 7.00 BSC
L2
E2 4.90 5.10
e 0.50 BSC
L 0.45 0.75
L2 0.25 BSC
M 0° 7°
M
GENERIC
MARKING DIAGRAM*
D2
BOTTOM VIEW
XXXXXXXXXX
XXXXXXXXXX
AWLYYWWG
RECOMMENDED
SOLDERING FOOTPRINT*
E2
9.36
48X
5.30 1.13
1
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb Free Package
5.30 9.36 *This information is generic. Please refer to
device data sheet for actual part marking.
1
0.50
PITCH
48X
0.29
DIMENSIONS: MILLIMETERS
*For additional information on our Pb Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
5
5 Page 
LV5239TA
Serial Bus Communication Specifications
1) Serial bus transfer timing conditions
Parameter
Cycle time
Data setup time
Data hold time
Pulse width
Symbol
tcy1
ts0
ts1
th0
th1
tw1L
tw1H
tw2L
Conditions
SCLK clock period
SDEN setup time relative to the rise of SCLK
SDATA setup time relative to the rise of SCLK
SDEN hold time relative to the fall of SCLK
SDATA hold time relative to the fall of SCLK
Low period pulse width of SCLK
High period pulse width of SCLK
Low period pulse width of SDEN
Min.
200
90
60
200
60
90
90
1
Typ.
-
-
-
-
-
-
-
-
Max.
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
s
2) 3-wire serial bus transfer formats
LV5239TA receives the command by communication format by 3 line type serial communication of SCLK,
SDATA, and SDEN.
When SCLK stops in “L” level
When SCLK stops in “H” level
Data length : 24bits
Clock frequency : 5MHz or less
When 24 SCLK clock signals have been input during the high period of SDEN, the SDATA is taken in at the rising
edge of SCLK.
Note: If the number of SCLK clock signals during the high period of SDEN is 23 or less, SDATA is not taken in. If it
is 25 or more, the register address is automatically incremented every time 1byte is taken in.
Data organization
The slave address is assigned by the first byte, and the register address on the serial map is specified by the next byte.
The third byte transfers the data to the address specified by the register address that was written by the second byte and
if the data subsequently continues even after this, the register address is automatically incremented for the fourth and
subsequent bytes. As a result, it is possible to send the data continuously from the specified addresses. Data of less than
one byte is ignored. However, when the address reaches 1fh, the next byte to be transferred becomes 00h.
www.onsemi.com
11
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| PDF Descargar | [ Datasheet LV5239TA.PDF ] | |
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