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PDF DA14583 Data sheet ( Hoja de datos )
| Número de pieza | DA14583 | |
| Descripción | Low Power Bluetooth Smart SoC | |
| Fabricantes | Dialog Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DA14583 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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DATASHEET - TARGET
MARCH 06, 2015 V1.1
DA14583
Low Power Bluetooth Smart SoC with Flash memory
General description
Memories
The DA14583 integrated circuit has a fully integrated
radio transceiver and baseband processor for Blue-
tooth® Smart. It can be used as a standalone applica-
tion processor or as a data pump in hosted systems.
1 Mbit Flash memory
32 kB One-Time-Programmable (OTP) memory
42 kB System SRAM
84 kB ROM
8 kB Retention SRAM
The DA14583 supports a flexible memory architecture,
Power management
including 1 Mbit of Flash memory, for storing Bluetooth
Integrated Buck mode DC-DC converter
profiles and custom application code, which can be
Embedded charge pump for Flash programming
updated over the air (OTA). The qualified Bluetooth
P0, P1, and P2 ports with 3.3 V tolerance
Smart protocol stack is stored in a dedicated ROM. All
software runs on the ARM® Cortex®-M0 processor via
Supports coin (typ. 3.0 V) battery cells
10-bit ADC for battery voltage measurement
a simple scheduler.
Digital controlled oscillators
The Bluetooth Smart firmware includes the L2CAP ser-
vice layer protocols, Security Manager (SM), Attribute
Protocol (ATT), the Generic Attribute Profile (GATT)
and the Generic Access Profile (GAP). All profiles pub-
lished by the Bluetooth SIG as well as custom profiles
are supported.
16 MHz crystal (±20 ppm max) and RC oscillator
32 kHz crystal (±50 ppm, ±500 ppm max) and
RCX oscillator
General purpose, Capture and Sleep timers
Digital interfaces
24 general purpose I/Os
2 UARTs with hardware flow control up to 1 MBd
The transceiver interfaces directly to the antenna and
SPI+™ interface
is fully compliant with the Bluetooth 4.1 standard.
I2C bus at 100 kHz, 400 kHz
The DA14583 has dedicated hardware for the Link
Layer implementation of Bluetooth Smart and interface
controllers for enhanced connectivity capabilities.
3-axes capable Quadrature Decoder
Analog interfaces
4-channel 10-bit ADC
Radio transceiver
Features
Fully integrated 2.4 GHz CMOS transceiver
Single wire antenna: no RF matching or RX/TX
Complies with Bluetooth V4.1, ETSI EN 300 328 and
switching required
EN 300 440 Class 2 (Europe), FCC CFR47 Part 15
Supply current at VBAT3V:
(US) and ARIB STD-T66 (Japan)
TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)
Processing power
0 dBm transmit output power
16 MHz 32 bit ARM Cortex-M0 with SWD inter-
-20 dBm output power in “Near Field Mode”
face -93 dBm receiver sensitivity
Dedicated Link Layer Processor
Packages:
AES-128 bit encryption Processor
QFN 40 pins, 5 mm x 5 mm
________________________________________________________________________________________________
System diagram
© 2014 Dialog Semiconductor
1 www.dialog-semiconductor.com
1 page  
Table 3: Pin Description
PIN NAME
TYPE
General Purpose I/Os
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P1_0
P1_1
P1_2
P1_3
P1_4/SW_CLK
P1_5/SWDIO
DIO
DIO
DIO
DIO
DIO
DIO
P2_0/SPI_CLK
P2_1
P2_2
P2_3/SPI_EN
P2_4/SPI_DO
P2_5
P2_6
P2_7
P2_8
P2_9/SPI_DI
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
P3_0 to P3_7
DIO
Debug interface
SWDIO/P1_5
DIO
Drive
(mA)
4.8
4.8
4.8
4.8
4.8
SW_CLK/P1_4 DIO
Clocks
XTAL16Mp
AI
XTAL16Mm
AO
XTAL32kp
AI
XTAL32km
AO
Quadrature decoder
QD_CHA_X
DI
QD_CHB_X
DI
QD_CHA_Y
DI
QD_CHB_Y
DI
QD_CHA_Z
DI
QD_CHB_Z
DI
SPI bus interface
SPI_CLK/P2_0
DO
SPI_DI/P2_9
DI
SPI_DO/P2_4
DO
4.8
Reset
state
(Note )
DESCRIPTION
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PU
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
I-PD
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
This signal is the JTAG clock by default
This signal is the JTAG data I/O by default
INPUT/OUTPUT with selectable pull up/down resistor. Pull-down
enabled during and after reset. General purpose I/O port bit or
alternate function nodes. Contains state retention mechanism
during power down.
Note: The specified pin assignment of the SPI interface is man-
datory for booting from internal Flash memory.
Not supported
I-PU
I-PD
INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and
control communication. Can also be used as a GPIO
INPUT JTAG clock signal. Can also be used as a GPIO
INPUT. Crystal input for the 16 MHz XTAL
OUTPUT. Crystal output for the 16 MHz XTAL
INPUT. Crystal input for the 32.768 kHz XTAL
OUTPUT. Crystal output for the 32.768 kHz XTAL
INPUT. Channel A for the X axis. Mapped on Px ports
INPUT. Channel B for the X axis. Mapped on Px ports
INPUT. Channel A for the Y axis. Mapped on Px ports
INPUT. Channel B for the Y axis. Mapped on Px ports
INPUT. Channel A for the Z axis. Mapped on Px ports
INPUT. Channel B for the Z axis. Mapped on Px ports
INPUT/OUTPUT. SPI Clock. Mapped on Px ports
INPUT. SPI Data input. Mapped on Px ports
OUTPUT. SPI Data output. Mapped on Px ports
© 2014 Dialog Semiconductor 5 Target - March 06, 2015 v1.1
5 Page 
• Interrupt or polled-mode operation
• Handles Bit and Byte waiting at both bus speeds
• Programmable SDA hold time
3.6.4 General purpose ADC
The DA14583 is equipped with a high-speed ultra low
power 10-bit general purpose Analog-to-Digital Con-
verter (GPADC). It can operate in unipolar (single
ended) mode as well as in bipolar (differential) mode.
The ADC has its own voltage regulator (LDO) of 1.2 V,
which represents the full scale reference voltage.
Features
• 10-bit dynamic ADC with 65 ns conversion time
• Maximum sampling rate 3.3 Msample/s
• Ultra low power (5 A typical supply current at
100 ksample/s)
• Single-ended as well as differential input with two
input scales
• Four single-ended or two differential external input
channels
• Battery monitoring function
• Chopper function
• Offset and zero scale adjust
• Common-mode input level adjust
3.6.6 Keyboard controller
The Keyboard controller can be used for debouncing
the incoming GPIO signals when implementing a key-
board scanning engine. It generates an interrupt to the
CPU (KEYBR_IRQ).
In parallel, five extra interrupt lines can be triggered by
a state change on 32 selectable GPIOs (GPIOx_IRQ).
3.6.5 Quadrature decoder
This block decodes the pulse trains from a rotary
encoder to provide the step and the direction of the
movement of an external device. Three axes (X, Y, Z)
are supported.
The integrated quadrature decoder can automatically
decode the signals for the X, Y and Z axes of a HID
input device, reporting step count and direction: the
channels are expected to provide a pulse train with 90
degrees phase difference; depending on whether the
reference channel is leading or lagging, the direction
can be determined.
This block can be used for waking up the chip as soon
as there is any kind of movement from the external
device connected to it.
Features
• Three 16-bit signed counters that provide the step
count and direction on each of the axes (X, Y and Z)
• Programmable system clock sampling at maximum
16 MHz.
• APB interface for control and programming
• Programmable source from P0, P1 and P2 ports
• Digital filter on the channel inputs to avoid spikes
© 2014 Dialog Semiconductor 11 Target - March 06, 2015 v1.1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DA14583.PDF ] | |
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