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Número de pieza | 74AUP1G58 | |
Descripción | Low-power configurable multiple function gate | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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No Preview Available ! 74AUP1G58
Low-power configurable multiple function gate
Rev. 7 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G58 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions AND, OR, NAND,
NOR, XOR, inverter and buffer. All inputs can be connected to VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G58 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 A (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
1 page NXP Semiconductors
74AUP1G58
Low-power configurable multiple function gate
9&&
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&
$
&
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DDE
Fig 8. 2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
9&&
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DDE
Fig 9. 2-input OR gate or 2-input NAND gate with
both inputs inverted
9&&
% &
%
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Fig 10. 2-input XOR gate
DDE
9&&
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Fig 11. Buffer
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DDE
9&&
Fig 12. Inverter
%
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DDE
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
0.5 +4.6 V
IIK
input clamping current
VI < 0 V
50 - mA
VI input voltage
[1] 0.5
+4.6 V
IOK output clamping current VO < 0 V
50 - mA
VO output voltage
Active mode and Power-down mode [1]
0.5
+4.6 V
IO output current
VO = 0 V to VCC
- 20 mA
ICC supply current
- 50 mA
74AUP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 24
5 Page NXP Semiconductors
12. Waveforms
74AUP1G58
Low-power configurable multiple function gate
9,
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90
90
*1'
92+
W 3+/
W 3/+
<RXWSXW
90
90
92/
92+
W 3/+
W 3+/
<RXWSXW
90
90
92/
DDE
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 13. Input A, B and C to output Y propagation delay times
Table 10. Measurement points
Supply voltage
Output
VCC
0.8 V to 3.6 V
VM
0.5 VCC
Input
VM
0.5 VCC
VI
VCC
tr = tf
3.0 ns
74AUP1G58
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 17 September 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 24
11 Page |
Páginas | Total 24 Páginas | |
PDF Descargar | [ Datasheet 74AUP1G58.PDF ] |
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