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Numéro de référence | 74AVC1T45 | ||
Description | Dual-supply voltage level translator/transceiver | ||
Fabricant | NXP Semiconductors | ||
Logo | |||
1 Page
74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Rev. 6 — 20 April 2016
Product data sheet
1. General description
The 74AVC1T45 is a single bit, dual supply transceiver with 3-state output that enables
bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction
control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can
be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for
translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH
on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to
A.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (< 1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
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Pages | Pages 25 | ||
Télécharger | [ 74AVC1T45 ] |
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