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STMicroelectronics - OCTAL D-TYPE LATCH

Numéro de référence 74LVC573A
Description OCTAL D-TYPE LATCH
Fabricant STMicroelectronics 
Logo STMicroelectronics 





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74LVC573A fiche technique
74LVC573A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
)|IOH| = IOL = 24mA (MIN) at VCC = 3V
t(ss PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
cs BALANCED PROPAGATION DELAYS:
utPLH tPHL
ds OPERATING VOLTAGE RANGE:
roVCC(OPR) = 1.65V to 3.6V (1.2V Data
PRetention)
s PIN AND FUNCTION COMPATIBLE WITH
te74 SERIES 573
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC573AMTR
74LVC573ATTR
les LATCH-UP PERFORMANCE EXCEEDS
o500mA (JESD 17)
outputs will follow the data input precisely or
bss ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
OMM > 200V
t(s) -DESCRIPTION
The 74LVC573A is a low voltage CMOS OCTAL
cD-TYPE LATCH fabricated with sub-micron silicon
dugate and double-layer metal wiring C2MOS
rotechnology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
Papplications.
teThese 8 bit D-Type latch are controlled by a latch
leenable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components. It has more speed performance at
3.3V than 5V AC/ACT family, combined with a
lower power consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
ObsoFigure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 3
1/13

PagesPages 13
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