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PDF TLV4946K Data sheet ( Hoja de datos )
| Número de pieza | TLV4946K | |
| Descripción | Value Optimized Hall Effect Latches | |
| Fabricantes | Infineon | |
| Logotipo |  |
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TLV4946K, TLV4946-2K
Value Optimized Hall Effect Latches for Industrial and Consumer
Applications
Datasheet
Rev1.1, 2010-08-02
Sense and Control
1 page  
TLV4946K, TLV4946-2K
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration and sensitive area (Top view, figure not to scale) . . . . . . . . . . . . . . . . . . . . . . . . 8
TLV4946K, TLV4946-2K Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Definition of the Magnetic Field direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Marking of the TLV4946K and TLV4946-2K and distance of the chip to the upper side . . . . . . . . 14
PG-SC59-3-5 Package Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Footprint PG-SC59-3-5 (SOT23 compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Datasheet
5 Rev1.1, 2010-08-02
5 Page 
3 Specification
3.1 Application circuit
TLV4946K, TLV4946-2K
Specification
QQ
GND
VS
GND
200Ω
VS
Figure 5 Application circuit
It is recommended to use a resistor of 200 Ω in the supply line for current limitation in the case of an overvoltage
pulse. Two capacitors of 4.7 nF enhance the EMC performance. The pull-up of 1.2 kΩ limits the current through
the output transistor.
3.2 Absolute Maximum Ratings
Stress above the maximum values listed in this section may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect the reliability of the device. Exceeding only
one of these values may cause irreversible damage to the device.
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Maximum Ambient Temperature TA
Maximum Junction Temperature TJ
Supply Voltage
VS
Supply current through protection IS
device
Output Voltage
Storage Temperature
Magnetic flux density
VOUT
TS
B
ESD Robustness HBM:
1.5 kΩ, 100 pF
V 1)
ESD,HBM
1) According to EIA/JESD22-A114-E
Min.
- 40
- 40
- 18
-50
- 0.7
- 40
–
–
Values
Typ. Max.
– 125
– 150
– 18
– 50
Unit
°C
°C
V
mA
– 18
V
– 150
°C
– unlimited mT
–4
kV
Note / Test Condition
Datasheet
11 Rev1.1, 2010-08-02
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet TLV4946K.PDF ] | |
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