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PDF AD7705 Data sheet ( Hoja de datos )
| Número de pieza | AD7705 | |
| Descripción | Sigma-Delta ADCs | |
| Fabricantes | Analog Devices | |
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FEATURES
AD7705: 2 fully differential input channel ADCs
AD7706: 3 pseudo differential input channel ADCs
16 bits no missing codes
0.003% nonlinearity
Programmable gain front end: gains from 1 to 128
3-wire serial interface
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt-trigger input on SCLK
Ability to buffer the analog input
2.7 V to 3.3 V or 4.75 V to 5.25 V operation
Power dissipation 1 mW maximum @ 3 V
Standby current 8 μA maximum
16-lead PDIP, 16-lead SOIC, and 16-lead TSSOP packages
GENERAL DESCRIPTION
The AD7705/AD7706 are complete analog front ends for low
frequency measurement applications. These 2-/3-channel devices
can accept low level input signals directly from a transducer and
produce serial digital output. The devices employ a Σ-Δ
conversion technique to realize up to 16 bits of no missing codes
performance. The selected input signal is applied to a
proprietary, programmable-gain front end based around an
analog modulator. The modulator output is processed by an on-
chip digital filter. The first notch of this digital filter can be pro-
grammed via an on-chip control register, allowing adjustment of
the filter cutoff and output update rate.
The AD7705/AD7706 devices operate from a single 2.7 V to
3.3 V or 4.75 V to 5.25 V supply. The AD7705 features two fully
differential analog input channels; the AD7706 features three
pseudo differential input channels.
Both devices feature a differential reference input. Input signal
ranges of 0 mV to 20 mV through 0 V to 2.5 V can be
incorporated on both devices when operating with a VDD of 5 V
and a reference of 2.5 V. They can also handle bipolar input
signal ranges of ±20 mV through ±2.5 V, which are referenced to
the AIN(−) inputs on the AD7705 and to the COMMON input
on the AD7706.
3 V/5 V, 1 mW, 2-/3-Channel,
16-Bit, Sigma-Delta ADCs
AD7705/AD7706
ANALOG
INPUT
CHANNELS
FUNCTIONAL BLOCK DIAGRAM
VDD REF IN(–) REF IN(+)
AD7705/AD7706
MAX
BUFFER
PGA
CHARGE
BALANCING
A/D CONVERTER
Σ -Δ
MODULATOR
A = 1 ≈ 128
DIGITAL FILTER
MCLK IN
MCLK OUT
CLOCK
GENERATION
SERIAL INTERFACE
REGISTER BANK
SCLK
CS
DIN
DOUT
GND
DRDY RESET
Figure 1.
The AD7705/AD7706 devices, with a 3 V supply and a 1.225 V
reference, can handle unipolar input signal ranges of 0 mV to
10 mV through 0 V to 1.225 V. The devices can accept bipolar
input ranges of ±10 mV through ±1.225 V. Therefore, the
AD7705/AD7706 devices perform all signal conditioning and
conversion for a 2-channel or 3-channel system.
The AD7705/AD7706 are ideal for use in smart, microcontroller,
or DSP-based systems. The devices feature a serial interface that
can be configured for 3-wire operation. Gain settings, signal
polarity, and update rate selection can be configured in software
using the input serial port. The parts contains self-calibration and
system calibration options to eliminate gain and offset errors on
the part itself or in the system. CMOS construction ensures very
low power dissipation, and the power-down mode reduces the
standby power consumption to 20 μW typ.
These parts are available in a 16-lead, wide body (0.3 inch),
plastic dual in-line package (DIP); a 16-lead, wide body
(0.3 inch), standard small outline (SOIC) package; and a low
profile, 16-lead, thin shrink small outline package (TSSOP).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD7705/AD7706
SPECIFICATIONS
VDD = 3 V or 5 V, REF IN(+) = 1.225 V with VDD = 3 V, and 2.5 V with VDD = 5 V; REF IN(−) = GND; MCLK IN = 2.4576 MHz, unless
otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity2
Unipolar Offset Error3
Unipolar Offset Drift4
Bipolar Zero Error3
Bipolar Zero Drift4
Positive Full-Scale Error3, 5
Full-Scale Drift4, 6
Gain Error3, 7
Gain Drift4, 8
Bipolar Negative Full-Scale Error2
Bipolar Negative Full-Scale Drift4
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Rejection (CMR)2
VDD = 5 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8 to 128
VDD = 3 V
Gain = 1
Gain = 2
Gain = 4
Gain = 8 to 128
Normal-Mode 50 Hz Rejection2
Normal-Mode 60 Hz Rejection2
Common-Mode 50 Hz Rejection2
Common-Mode 60 Hz Rejection2
Absolute/Common-Mode REF IN
Voltage2
Absolute/Common-Mode AIN
Voltage2, 9, 10
Absolute/Common-Mode AIN
Voltage2, 9
AIN DC Input Current2
AIN Sampling Capacitance2
AIN Differential Voltage Range11
B Version1
16
See Table 5 and
Table 7
±0.003
0.5
0.5
0.1
0.5
0.5
±0.003
1
0.6
96
105
110
130
105
110
120
130
98
98
150
150
GND to VDD
GND − 100 mV
VDD + 30 mV
GND + 50 mV
VDD − 1.5 V
1
10
0 to +VREF/gain12
±VREF/gain
Unit Conditions/Comments
Bits min
Guaranteed by design, filter notch < 60 Hz
Depends on filter cutoffs and selected gain
% of FSR max Filter notch < 60 Hz, typically ±0.0003%
μV/°C typ
μV/°C typ
μV/°C typ
For gains 1, 2, and 4
For gains 8, 16, 32, 64, and 128
μV/°C typ
ppm of FSR/°C
typ
% of FSR typ
μV/°C typ
μV/°C typ
Typically ±0.001%
For gains of 1 to 4
For gains of 8 to 128
Specifications for AIN and REF IN, unless otherwise
noted
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
V min to V max
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
For filter notches of 25 Hz, 50 Hz, ±0.02 × fNOTCH
For filter notches of 20 Hz, 60 Hz, ±0.02 × fNOTCH
V min
BUF bit of setup register = 0
V max
V min
BUF bit of setup register = 1
V max
nA max
pF max
nom
nom
Unipolar input range (B/U bit of setup register = 1)
Bipolar input range (B/U bit of setup register = 0)
Rev. C | Page 5 of 44
5 Page 
AD7705/AD7706
Pin No.
14
Mnemonic
AD7705 AD7706
DIN DIN
15 VDD
VDD
16 GND GND
Description
Serial Data Input. Serial data is written to the input shift register on the part. Data from the input shift
register is transferred to the setup register, clock register, or communication register, depending on
the register selection bits of the communication register.
Supply Voltage. 2.7 V to 5.25 V operation.
Ground Reference Point for the AD7705/AD7706 Internal Circuitry.
Rev. C | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7705.PDF ] | |
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