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PDF AD7703 Data sheet ( Hoja de datos )
| Número de pieza | AD7703 | |
| Descripción | 20-Bit A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7703 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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LC2MOS
20-Bit A/D Converter
AD7703
FEATURES
Monolithic 16-Bit ADC
0.0015% Linearity Error
On-Chip Self-Calibration Circuitry
Programmable Low-Pass Filter
0.1 Hz to 10 Hz Corner Frequency
0 V to +2.5 V or ؎2.5 V Analog Input Range
4 kSPS Output Data Rate
Flexible Serial Interface
Ultralow Power
APPLICATIONS
Industrial Process Control
Weigh Scales
Portable Instrumentation
Remote Data Acquisition
FUNCTIONAL BLOCK DIAGRAM
DVDD 15
AVDD 14
AVSS
7
DVSS
6
SC1
4
SC2
17
AD7703
CALIBRATION
SRAM
CALIBRATION
MICROCONTROLLER
13 CAL
AIN 9
VREF 10
AGND 8
DGND 5
20-BIT CHARGE BALANCE A/D
CONVERTER
ANALOG
MODULATOR
6-POLE GAUSSIAN
LOW-PASS
DIGITAL FILTER
12 BP/UP
11 SLEEP
CLOCK
GENERATOR
SERIAL INTERFACE
LOGIC
20 SDATA
19 SCLK
32
CLKIN CLKOUT
1
MODE
16
CS
18
DRDY
GENERAL DESCRIPTION
The AD7703 is a 20-bit ADC that uses a S-D conversion tech-
nique. The analog input is continuously sampled by an analog
modulator whose mean output duty cycle is proportional to the
input signal. The modulator output is processed by an on-chip
digital filter with a six-pole Gaussian response, which updates the
output data register with 16-bit binary words at word rates up to
4 kHz. The sampling rate, filter corner frequency, and output
word rate are set by a master clock input that may be supplied
externally, or by a crystal controlled on-chip clock oscillator.
The inherent linearity of the ADC is excellent and endpoint accu-
racy is ensured by self-calibration of zero and full scale, which
may be initiated at any time. The self-calibration scheme can
also be extended to null system offset and gain errors in the input
channel.
The output data is accessed through a flexible serial port, which
has an asynchronous mode compatible with UARTs and two
synchronous modes suitable for interfacing to shift registers or
the serial ports of industry-standard microcontrollers.
CMOS construction ensures low power dissipation, and a power-
down mode reduces the idle power consumption to only 10 µW.
PRODUCT HIGHLIGHTS
1. The AD7703 offers 20-bit resolution coupled with outstanding
0.0003% accuracy.
2. No missing codes ensures true, usable, 20-bit dynamic range,
removing the need for programmable gain and level-setting
circuitry.
3. The effects of temperature drift are eliminated by on-chip
self-calibration, which removes zero and gain error. External
circuits can also be included in the calibration loop to remove
system offsets and gain errors.
4. Flexible synchronous/asynchronous interface allows the
AD7703 to interface directly to the serial ports of industry-
standard microcontrollers and DSP processors.
5. Low operating power consumption and an ultralow power
standby mode make the AD7703 ideal for loop-powered
remote sensing applications, or battery-powered portable
instruments.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD7703
TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = +5 V ؎ 10%; AVSS = DVSS = –5 V ؎ 10%; AGND = DGND = O V;
fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)
Parameter
Limit at TMIN, TMAX Limit at TMIN, TMAX
(A, B Versions)
(S, T Versions) Unit
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t1
t2
t36
200
5
200
5
50
50
0
50
1000
200
5
200
5
50
50
0
50
1000
kHz min
MHz max
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
Master Clock Frequency: Internal Gate Oscillator
Typically 4.096 MHz
Master Clock Frequency: Externally Supplied
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
SSC MODE
t47
t5
t6
7
t8
t98
t108, 9
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
3/fCLKIN
100
250
300
790
l/fCLKIN + 200
4/fCLKIN + 200
ns max
ns max
ns min
ns max
ns max
ns max
ns max
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/fCLKIN + 100 ns typ)
CS High to Hi-Z Delay
SEC MODE
fSCLK
t11
t12
t137, 10
t1411
t158
t168
5
35
160
160
150
250
200
5 MHz max Serial Clock Input Frequency
35 ns min SCLK Input High Pulsewidth
160 ns min SCLK Low Pulsewidth
160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.
150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
250 ns max CS High to Hi-Z Delay
200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with t r = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 to 6.
3CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
4The AD7703 is production tested with fCLKIN at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
5Specified using 10% and 90% points on waveform of interest.
6In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
7t4 and t13 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
8t9, t10, t15, and t16 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
9If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
10If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
11SDATA is clocked out on the falling edge of the SCLK input.
Specifications subject to change without notice.
IOL
1.6mA
TO
OUTPUT
PIN CL
100pF
+2.1V
IOH
200A
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
–4–
CAL
SC1, SC2
t1 t2
SC1, SC2 VALID
Figure 2. Calibration Control Timing
CLKIN
SLEEP
t3
Figure 3. Sleep Mode Timing
REV. E
5 Page 
AD7703
Initiating Calibration
Table III illustrates the calibration modes available in the AD7703.
Not shown in the table is the function of the BP/UP pin, which
determines whether the converter has been calibrated to mea-
sure bipolar or unipolar signals. A calibration step is initiated by
bringing the CAL pin high for at least four CLKIN cycles and
then bringing it low again. The states of SC1 and SC2 along
with the BP/UP pin will determine the type of calibration to be
performed. All three signals should be stable before the CAL
pin is taken positive. The SC1 and SC2 inputs are latched when
CAL goes high. The BP/UP input is not latched and, therefore,
must remain in a fixed state throughout the calibration and
measurement cycles. Any time the state of the BP/UP is changed,
a new calibration cycle must be performed to enable the AD7703
to function properly in the new mode.
When a calibration step is initiated, the DRDY signal will go high
and remain high until the step is finished. Table III shows the
number of clock cycles each calibration requires. Once a calibra-
tion step is initiated, it must finish before a new calibration step
can be executed. In the two step system calibration mode, the
offset calibration step must be initiated before initiating the gain
calibration step.
When self-calibration is completed, DRDY falls and the output
port is updated with a data-word that represents the analog input
signal. When a system calibration step is completed, DRDY will
fall and the output port will be updated with the appropriate data
value (all 0s for the zero-scale point and all 1s for the full-scale
point). In the system calibration mode, the digital filter must
settle before the output code will represent the value of the
analog input signal. Tables IV and V indicate the output code
size and output coding of the AD7703 in its various modes. In
these tables, SOFF is the measured system offset in volts and
SGAIN is the measured system gain at the full-scale point in volts.
Span and Offset Limits
Whenever a system calibration mode is used, there are limits
on the amount of offset and span that can be accommodated.
The range of input span in both the Unipolar and Bipolar
modes has a minimum value of 0.8 VREF and a maximum
value of 2(VREF + 0.1 V).
The amount of offset that can be accommodated depends on
whether the Unipolar or Bipolar mode is being used. In Unipolar
mode, the system calibration modes can handle a maximum
offset of 0.2 VREF and a minimum offset of –(VREF + 0.1 V).
Therefore the AD7703 in the Unipolar mode can be calibrated
to mimic bipolar operation.
Table III. Calibration Truth Table*
CAL SC1 SC2
Calibration
Type
Zero-Scale
Calibration
Full-Scale
Calibration
Sequence
Calibration
Time
00
11
01
10
Self-Calibration
System Offset
System Gain
System Offset
VAGND
AIN
AIN
VREF
AIN
VREF
One Step
First Step
Second Step
One Step
3,145,655 Clock Cycles
1,052,599 Clock Cycles
1,068,813 Clock Cycles
2,117,389 Clock Cycles
*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other
modes, DRDY falls as the device begins to settle.
Table IV. Output Code Size After Calibration
Calibration Mode Zero Scale
Self-Calibration
VAGND
System Calibration SOFF
Gain Factor
VREF
SGAIN
Unipolar
(VREF –VAGND )
1048576
(SGAIN – SOFF )
1048576
1 LSB
Bipolar
2(VREF –VAGND )
1048576
2(SGAIN – SOFF )
1048576
–10–
REV. E
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD7703.PDF ] | |
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