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PDF STM8S103K3 Data sheet ( Hoja de datos )
| Número de pieza | STM8S103K3 | |
| Descripción | 16 MHz STM8S 8-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STM8S103F2 STM8S103F3
STM8S103K3
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash,
data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Datasheet - production data
Features
Core
• 16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
• Extended instruction set
Memories
• Program memory: 8 Kbyte Flash; data
retention 20 years at 55 °C after 10 kcycle
• Data memory: 640 byte true data EEPROM;
endurance 300 kcycle
• RAM: 1 Kbyte
Clock, reset and supply management
• 2.95 to 5.5 V operating voltage
• Flexible clock control, 4 master clock sources
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low-power 128 kHz RC
• Clock security system with clock monitor
• Power management:
– Low-power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
• Permanently active, low-consumption power-
on and power-down reset
Interrupt management
• Nested interrupt controller with 32 interrupts
• Up to 27 external interrupts on 6 vectors
Timers
• Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
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• 16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
• 8-bit basic timer with 8-bit prescaler
• Auto wake-up timer
• Window watchdog and independent watchdog
timers
Communication interfaces
• UART with clock output for synchronous
operation, SmartCard, IrDA, LIN master mode
• SPI interface up to 8 Mbit/s
• I2C interface up to 400 kbit/s
Analog to digital converter (ADC)
• 10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
• Up to 28 I/Os on a 32-pin package including
21 high sink outputs
• Highly robust I/O design, immune against
current injection
Unique ID
• 96-bit unique key for each device
October 2016
This is information on a product in full production.
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STM8S103F2 STM8S103F3 STM8S103K3
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
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Table 20.
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Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
STM8S103F2/x3 access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Legend/abbreviations for pin description tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM8S103K3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM8S103F2 and STM8S103F3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM8S103K3 alternate function remapping bits for 32-pin devices . . . . . . . . . . . . . . . . . . 47
STM8S103Fx alternate function remapping bits for 20-pin devices . . . . . . . . . . . . . . . . . . 48
Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 55
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 56
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 58
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 60
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
ADC accuracy with RAIN< 10 kΩ, VDD= 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
ADC accuracy with RAIN< 10 kΩ, VDD= 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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STM8S103F2 STM8S103F3 STM8S103K3
3 Block diagram
Figure 1. STM8S103F2/x3 block diagram
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STM8S103K3.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
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