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PDF HEF4094B-Q100 Data sheet ( Hoja de datos )
| Número de pieza | HEF4094B-Q100 | |
| Descripción | 8-stage shift-and-store register | |
| Fabricantes | NXP Semiconductors | |
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HEF4094B-Q100
8-stage shift-and-store register
Rev. 3 — 4 July 2013
Product data sheet
1. General description
The HEF4094B-Q100 is an 8-stage serial shift register. It has a storage latch associated
with each stage for strobing data from the serial input to parallel buffered 3-state outputs
QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is
shifted on positive-going clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR) input is HIGH. Data in the
storage register appears at the outputs whenever the output enable (OE) signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of
HEF4094B-Q100 devices. Serial data is available at QS1 on positive-going clock edges to
allow high-speed operation in cascaded systems with a fast clock rise time. The same
serial data is available at QS2 on the next negative going clock edge. This is used for
cascading HEF4094B-Q100 devices when the clock has a slow rise time.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Connect unused inputs to VDD, VSS, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
1 page  
NXP Semiconductors
HEF4094B-Q100
8-stage shift-and-store register
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
Fig 6. Timing diagram
Z-state
Z-state
001aaf117
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter
Conditions
Min Max
Unit
VDD supply voltage
IIK input clamping current
VI input voltage
VI < 0.5 V or VI > VDD + 0.5 V
0.5
-
0.5
+18
10
VDD + 0.5
V
mA
V
IOK output clamping current
II/O input/output current
VO < 0.5 V or VO > VDD + 0.5 V - 10 mA
- 10 mA
IDD
Tstg
Tamb
Ptot
supply current
storage temperature
ambient temperature
total power dissipation
-
65
40
[1] -
50
+150
+125
500
mA
C
C
mW
P power dissipation
per output
- 100 mW
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VDD
VI
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage
input voltage
ambient temperature
in free air
input transition rise and fall rate
VDD = 5 V
VDD = 10 V
VDD = 15 V
Min Typ Max
Unit
3 - 15 V
0-
40 -
VDD
+125
V
C
- - 3.75 s/V
- - 0.5 s/V
- - 0.08 s/V
HEF4094B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
5 of 18
5 Page 
NXP Semiconductors
HEF4094B-Q100
8-stage shift-and-store register
a. Input waveform
VI
negative
pulse
0V
VI
positive
pulse
0V
90 %
10 %
VM
10 %
tf
tr
90 %
VM
tW
90 %
VM
10 %
tr
tf
90 %
VM
10 %
tW 001aaj781
VI
G
VDD
DUT
VEXT
VO RL
RT CL
001aaj915
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 11. Test circuit
Table 10. Test data
Supply voltage Input
VDD
5 V to 15 V
VI
VSS or VDD
tr, tf
20 ns
VEXT
tPHL, tPLH
open
tPHZ, tPZH
VSS
tPLZ, tPZL
VDD
Load
CL
50 pF
RL
1 k
HEF4094B_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
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