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PDF PN7360 Data sheet ( Hoja de datos )
| Número de pieza | PN7360 | |
| Descripción | NFC Cortex-M0 microcontroller | |
| Fabricantes | NXP Semiconductors | |
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PN746X_736X
NFC Cortex-M0 microcontroller
Rev. 3.1 — 5 April 2016
369231
Product data sheet
COMPANY PUBLIC
1. General description
The PN7462 family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers
offering high performance and low power consumption. It has a simple instruction set and
memory addressing along with a reduced code size compared to existing architectures.
PN7462 family offers all in one solutions, with features such as NFC, microcontroller,
optional contact smart card reader, and software in a single chip. It operates at CPU
frequencies of up to 20 MHz.
The family includes the following derivatives to fit every specific need:
• PN7462: NFC microcontroller, 160 kB Flash memory, and an ISO 7816/EMVCo
contact interface
• PN7362: NFC microcontroller with 160 kB Flash memory
• PN7360: NFC microcontroller with 80 kB Flash memory
The peripheral complement of the PN7462 family microcontrollers includes 160/80 kB of
flash memory, 12 kB of SRAM data memory and 4 kB EEPROM. It also includes one host
interface with either high-speed mode I2C-bus, SPI, USB or high-speed UART, and two
master interfaces, SPI and fast-mode plus I2C-bus. Four general-purpose counter/timers,
a random number generator, one CRC coprocessor and up to 21 general-purpose I/O
pins are also available.
The PN7462 family NFC microcontrollers offer a one chip solution to build contactless
applications. It is equipped with a highly integrated high-power output NFC-IC for
contactless communication at 13.56 MHz enabling EMV-compliance on RF level, without
additional external active components.
PN7462 family supports the following operating modes:
• ISO/IEC 14443-A and B, MIFARE
• JIS X 6319-4 (comparable with FeliCa scheme)
• ISO/IEC 15693, ICODE, ISO/IEC 18000-3 mode 3
• NFC protocols - tag reader/writer, P2P
• ISO/IEC 14443- type A card emulation
• EMVCo compliance
By integrating an ISO/IEC 7816 interface on a single chip in the PN7462, it provides a
solution for dual interface smart card readers. PN7462 contact interface offers a high level
of security for the card by performing current limiting, short-circuit detection, ESD
1 page  
NXP Semiconductors
PN746X_736X
NFC Cortex-M0 microcontroller
Table 1. Quick reference data …continued
Operating range: 40 C to +85 C unless specified; contact interface: VDDP(VBUSP) = VDDP(VBUS); contactless interface:
internal LDO not used
Symbol
Parameter
Conditions
Min Typ Max Unit
IDD(TVDD)
TVDD supply current on pin TVDD_IN; maximum
supported current by the
contactless interface
- - 250 mA
VCC
supply voltage
contact card
class A; ICC < 60 mA
class B; ICC < 50 mA
class C; ICC < 30 mA
ICC
supply current
contact card
class A cards
4.75 5
2.85 3
1.71 1.8
--
5.25 V
3.15 V
1.89 V
60 mA
class B cards
- - 55 mA
class C cards
- - 35 mA
Pmax
maximum power
dissipation
- - 1050 mW
Tamb
ambient temperature JEDEC PCB
40 -
+85 C
5. Ordering information
The PN7462 family includes the following products:
PN7462AU: Full feature set and memory available
PN7362AU: Full memory available, no contact interface
PN7360AU: Memory limited to 80 kB, and no contact interface.
The table below lists the ordering information for these three products.
Table 2. Ordering information
Type number
Package
Name
Description
Version
PN7462AUHN
HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-4
body 9 9 0.85 mm
PN7362AUHN
HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-4
body 9 9 0.85 mm
PN7360AUHN
HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; SOT804-4
body 9 9 0.85 mm
PN746X_736X
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 April 2016
369231
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 86
5 Page 
NXP Semiconductors
PN746X_736X
NFC Cortex-M0 microcontroller
8.2.3.1 Memory mapping
The SRAM memory mapping is shown in Figure 5.
5$0B6\VB(QG [)))
5$0B6\VB6WDUW [)
5$0B6<67(0
5(6(59('
%\WHV
5$086(55:
%\WHV
5$0B8VHUB6WDUW [
5$0B8VHUB52B6WDUW [
Fig 5. SRAM memory mapping
5(6(59('
%\WHV
DDD
8.2.4 ROM
The PN7462 contains 40 kB of on-chip ROM memory. The on-chip ROM contains
bootloader, USB mass storage primary download and the following Application
Programming Interfaces (APIs):
• In-Application Programming (IAP) support for flash
• Lifecycle management of debug interface, code write protection of flash memory and
USB mass storage primary download
• USB descriptor configuration
• Configuration of time-out and source of pad supply
8.2.5 Memory map
The PN7462 incorporates several distinct memory regions. Figure 6 shows the PN7462
memory map, from the user program perspective, following reset.
The APB peripheral area is 512 kB in size, and is divided to allow up to 32 peripherals.
Only peripherals from 0 to 15 are accessible. Each peripheral is allocated 16 kB, which
simplifies the address decoding for the peripherals. APB memory map is described in
Figure 7.
PN746X_736X
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 — 5 April 2016
369231
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 86
11 Page | ||
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| PDF Descargar | [ Datasheet PN7360.PDF ] | |
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