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AT49F040A fiches techniques PDF

ATMEL Corporation - 5-volt only in-system reprogrammable Flash memory

Numéro de référence AT49F040A
Description 5-volt only in-system reprogrammable Flash memory
Fabricant ATMEL Corporation 
Logo ATMEL Corporation 





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AT49F040A fiche technique
Features
Single-voltage Operation
– 5V Read
– 5V Reprogramming
Fast Read Access Time – 55 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Eight Main Memory Blocks (One 32K Bytes, Seven 64K Bytes)
Fast Erase Cycle Time – 6 Seconds
Byte-by-Byte Programming – 20 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 20 mA Active Current
– 70 µA CMOS Standby Current
Typical 10,000 Write Cycles
Green (Pb/Halide-free) Packaging Option
4-megabit
(512K x 8)
5-volt Only
Flash Memory
AT49F040A
1. Description
The AT49F040A is a 5-volt only in-system reprogrammable Flash memory. Its
4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 110 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 70 µA. To
allow for simple in-system reprogrammability, the AT49F040A does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus conten-
tion. Reprogramming the AT49F040A is performed by erasing a block of data and
then programming on a byte-by-byte basis. The byte programming time is a fast 20
µs. The end of a program cycle can be optionally detected by the DATA polling fea-
ture. Once the end of a byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program and erase cycles is in
excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device inter-
nally controls the erase operations. There are two 8K byte parameter block sections,
eight main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a repro-
gramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is perma-
nently protected from being reprogrammed.
3359C–FLASH–3/05

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