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PDF IS43QR16256A Data sheet ( Hoja de datos )
| Número de pieza | IS43QR16256A | |
| Descripción | 4Gb DDR4 SDRAM | |
| Fabricantes | ISSI | |
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IS43/46QR16256A
IS43/46QR85120A
512Mx8, 256Mbx16 4Gb DDR4 SDRAM
FEATURES
PRELIMINARY INFORMATION
JULY 2016
• Standard Voltage: VDD = VDDQ = 1.2V, VPP=2.5V
• High speed data transfer rates with system frequency
up to 2666 Mbps
• Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
• DRAM access bandwidth
- Separated IO gating structures by Bank Groups
- Self Refresh Abort
- Fine Granularity Refresh
• Signal Synchronization
- Write Leveling via MR settings
- Read Leveling via MPR
• Reliability & Error Handling
- Command/Address Parity
- Data bus Write CRC
- MPR readout
- Boundary Scan (x16)
• Speed Grade (CL-TRCD-TRP)
- 2133Mbps / 15-15-15 (-093P)
- 2400Mbps / 16-16-16 (-083R)
- 2666Mbps / 18-18-18 (-075U)
• Signal Integrity
- Internal VREFDQ Training
- Read Preamble Training
- Gear Down Mode
- Per DRAM Adressability
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Data bus Inversion (DBI)
- ZQ Calibration for DS/ODT impedance accuracy via external
ZQ pad (240 ohm +/- 1%)
• Power Saving and efficiency
- POD with VDDQ termination
- Command/Address Latency (CAL)
- Maximum Power Saving
- Low power Auto Self Refresh (LPASR)
• Operating Temperature
- Commercial ( Tc = 0 oC to + 95 oC)
- Industrial ( Tc = -40 oC to + 95oC)
- Automotive A1 ( Tc = -40 oC to + 95 oC)
- Automotive A2 ( Tc = -40 oC to + 105 oC)
PPROGRAMMABLE FUNCTIONS
• Output Driver Impedance (34/48)
• CAS Write Latency (9/0/11/12/14/16/18)
• Additive Latency (0/CL-1/CL-2)
• CS# to Command Address (3/4/5/6/8)
• Burst Type (Sequential/Interleaved)
• Write Recovery Time (10/12/14/16/18/20/24)
• Read Preamble (1T/2T)
• Write Preamble (1T/2T)
• Burst Length (BL8/BC4/BC4 or 8 on the fly)
Options
• Configuration: 512Mx8, 256Mx16
• Package:
- 96-ball FBGA (9mm x 13mm, 0.8mm ball pitch) for x16
- 78-ball FBGA (9mm x 11mm, 0.8mm ball pitch) for x8
ADDRESS TABLE
Parameter
512M x8
256M x16
Row Addressing
A0-A14
A0-A14
Column Addressing A0-A9
A0-A9
Bank Addressing
BA0-BA1
BA0-BA1
Bank Groups
BG0-BG1
BG0-BG1
Page size
1KB 2KB
tRFC
260ns
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A, 06/22/2016
1
1 page  
IS43/46QR16256A
IS43/46QR85120A
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A, 06/22/2016
5
5 Page 
IS43/46QR16256A
IS43/46QR85120A
VDD Slew Rate
Symbol
Min
Max
Units
NOTE
VDD_sl
0.004
600
V/ms
VDD_on
200 ms
1,2
3
NOTE 1
NOTE 2
NOTE 3
Measurement made between 300mV and 80% VDD (minimum level).
The DC bandwidth is limited to 20MHz
Maximum time to ramp VDD from 300 mV to VDD minimum.
Integrated Silicon Solution, Inc. - www.issi.com
Rev. 0A, 06/22/2016
11
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