PDF IS61LPS12836EC Data sheet ( Hoja de datos )

Número de pieza	IS61LPS12836EC
Descripción	SINGLE CYCLE DESELECT SRAM
Fabricantes	ISSI
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IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM OCTOBER 2015 FEATURES  Internal self-timed write cycle  Individual Byte Write Control and Global Write  Clock controlled, registered address, data and control  Burst sequence control using MODE input  Three chip enable option for simple depth expansion and address pipelining  Common data inputs and data outputs  Auto Power-down during deselect  Single cycle deselect  Snooze MODE for reduced-power standby  JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages  Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)  JTAG Boundary Scan for BGA packages  Industrial and Automotive temperature support  Lead-free available  Error Detection and Error Correction FAST ACCESS TIME Symbol tKQ tKC fMAX Parameter Clock Access Time Cycle time Frequency DESCRIPTION The 4Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LPS/VPS12836EC are organized as 131,072 words by 36bits. The IS61(64)LPS/VPS12832EC are organized as 131,072 words by 32bits. The IS61(64)LPS/VPS25618EC are organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive- edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (/BWE) input combined with one or more individual byte write signals (/BWx). In addition, Global Write (/GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either /ADSP (Address Status Processor) or /ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the /ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order. Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. -250 2.6 4 250 -200 3.1 5 200 Units ns ns MHz Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com Rev. D1 10/5/2015 1 1 page IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 256K x 18, 165-Ball BGA (Top View) 1 23 4 A NC A B NC A C NC NC D NC DQb E NC DQb F NC DQb G NC DQb H NC J DQb VSS NC K DQb NC L DQb NC M DQb NC N DQPb NC P NC NC R MODE NC /CE CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A /BWb NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 5 NC /BWa VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 /CE2 CLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC A1* A0* 7 /BWE /GW VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK 8 /ADSC /OE VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A A 9 /ADV /ADSP VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 A A NC NC NC NC NC NC DQa DQa DQa DQa NC A A 11 A NC DQPa DQa DQa DQa DQa ZZ NC NC NC NC NC NC A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. Bottom View 165-Ball, 13 mm x 15mm BGA 11 x 15 Ball Array PIN DESCRIPTIONS Symbol Pin Name CLK Synchronous Clock A0,A1 Synchronous Burst Address Inputs A Synchronous Address Inputs /ADV Synchronous Burst Address Advance /ADSP /ADSC MODE Synchronous Address Status Processor Synchronous Address Status Controller Burst Sequence Selection /CE,CE2,/CE2 Synchronous Chip Enable /BWE Synchronous Byte Write Enable /BWx (x=a-b) Synchronous Byte Write Inputs /GW Synchronous Global Write Enable /OE Asynchronous Output Enable DQx Synchronous Data Inputs/Outputs DQPx Synchronous Parity Data I/O TCK,TDI,TDO,TMS JTAG Pins ZZ Asynchronous Power Sleep Mode NC No Connect VDD Power Supply VDDQ I/O Power Supply VSS Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. D1 10/2/2015 5 5 Page IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 256K x 18, 100PIN QFP (Top View) NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 256K x 18 80 A 79 NC 78 NC 77 VDDQ 76 VSS 75 NC 74 DQPa 73 DQa 72 DQa 71 VSS 70 VDDQ 69 DQa 68 DQa 67 VSS 66 NC 65 VDD 64 ZZ 63 DQa 62 DQa 61 VDDQ 60 VSS 59 DQa 58 DQa 57 NC 56 NC 55 VSS 54 VDDQ 53 NC 52 NC 51 NC Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol CLK Pin Name Synchronous Clock A0,A1 Synchronous Burst Address Inputs A Synchronous Address Inputs /ADV Synchronous Burst Address Advance /ADSP Synchronous Address Status Processor /ADSC Synchronous Address Status Controller MODE Burst Sequence Selection /CE,CE2,/CE2 Synchronous Chip Enable /BWE Synchronous Byte Write Enable /BWx (x=a-b) Synchronous Byte Write Inputs Symbol /GW /OE DQx DQPx ZZ NC VDD VDDQ VSS Pin Name Synchronous Global Write Enable Asynchronous Output Enable Synchronous Data Inputs/Outputs Synchronous Parity Data I/O Asynchronous Power Sleep Mode No Connect Power Supply I/O Power Supply Ground Integrated Silicon Solution, Inc.- www.issi.com Rev. D1 10/2/2015 11 11 Page

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