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PDF IS67WVE1M16TALL Data sheet ( Hoja de datos )
| Número de pieza | IS67WVE1M16TALL | |
| Descripción | 16Mb Async/Page PSRAM | |
| Fabricantes | ISSI | |
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IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
16Mb Async/Page PSRAM
NOVEMBER 2015
Overview
The IS66/67WVE1M16EALL/BLL/CLL and IS66/67WVE1M16TALL/BLL/CLL are integrated memory device
containing 16Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 1M
words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where
data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby
current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate
power supply from the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 60ns, 70ns
Intrapage Read access : 25ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 23mA
Standby < 150 µA (max.)
Deep power-down (DPD)
ALL/CLL: < 3µA (Typ)
BLL: < 10µA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Packages:
48-ball TFBGA, 48-pin TSOP-I
Notes :
1. The 48-pin TSOP-I package option is not yet available. Please contact SRAM marketing at [email protected] for
additional information.
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. C | Oct. 2015
www.issi.com - [email protected]
1
1 page  
IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VSS
VSSQ
DQ0~DQ15
A0~A19
LB#
UB#
CE#
OE#
WE#
ZZ#
Type
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Description
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
Data Inputs/Outputs (DQ0~DQ15)
Address Input (A0~A19)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
Write Enable
Sleep enable : When ZZ# is LOW, the CR can be loaded, or the device
can enter one of two low-power modes ( DPD or PAR).
ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V
BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V
Rev. C | Oct. 2015
www.issi.com - [email protected]
5
5 Page 
IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Low-Power Feature
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to
perform the DRAM refresh operation. Standby operation occurs when CE# and ZZ# are HIGH.
The device will enter a reduced power state upon completion of a READ or WRITE
operations when the address and control inputs remain static for an extended period of time.
This mode will continue until a change occurs to the address or control inputs.
Temperature Compensated Refresh
Temperature compensated refresh (TCR) is used to adjust the refresh rate depending on the
device operating temperature. DRAM technology requires more frequent refresh operations to
maintain data integrity as temperatures increase. More frequent refresh is required due to the
increased leakage of the DRAM's capacitive storage elements as temperatures rise. A decreased
refresh rate at lower temperatures will result in a savings in standby current.
TCR allows for adequate refresh at four different temperature thresholds: +15°C, +45°C, +70°C,
and +85°C. The setting selected must be for a temperature higher than the case temperature of
the device. If the case temperature is +50°C, the system can minimize self refresh current
consumption by selecting the +70°C setting. The +15°C and +45°C settings would result in
inadequate refreshing and cause data corruption.
Rev. C | Oct. 2015
www.issi.com - [email protected]
11
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| PDF Descargar | [ Datasheet IS67WVE1M16TALL.PDF ] | |
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