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PDF LT1765-1.8 Data sheet ( Hoja de datos )
| Número de pieza | LT1765-1.8 | |
| Descripción | 1.25MHz Step-Down Switching Regulator | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Monolithic 3A, 1.25MHz
Step-Down Switching Regulator
FEATURES
n 3A Switch in a Thermally Enhanced 16-Lead
TSSOP or 8-Lead SO Package
n Constant 1.25MHz Switching Frequency
n Wide Operating Voltage Range: 3V to 25V
n High Efficiency 0.09Ω Switch
n 1.2V Feedback Reference Voltage
n Uses Low Profile Surface Mount Components
n Low Shutdown Current: 15μA
n Synchronizable to 2MHz
n Current Mode Loop Control
n Constant Maximum Switch Current Rating at
All Duty Cycles*
n Available in 8-Lead SO and 16-Lead Thermally
Enhanced TSSOP Packages
APPLICATIONS
n DSL Modems
n Portable Computers
n Regulated Wall Adapters
n Battery-Powered Systems
n Distributed Power
DESCRIPTION
The LT®1765 is a 1.25MHz monolithic buck switching
regulator. A high efficiency 3A, 0.09Ω switch is included
on the die together with all the control circuitry required
to construct a high frequency, current mode switching
regulator. Current mode control provides fast transient
response and excellent loop stability.
New design techniques achieve high efficiency at high
switching frequencies over a wide operating voltage
range. A low dropout internal regulator maintains con-
sistent performance over a wide range of inputs from
24V systems to Li-Ion batteries. An operating supply
current of 1mA improves efficiency, especially at lower
output currents. Shutdown reduces quiescent current to
15μA. Maximum switch current remains constant at all
duty cycles. Synchronization allows an external logic level
signal to increase the internal oscillator into the range of
1.6MHz to 2MHz.
Full cycle-by-cycle current control and thermal shutdown
are provided. High frequency operation allows the reduc-
tion of input and output filtering components and permits
the use of chip inductors.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
*Patent Pending
TYPICAL APPLICATION
5V to 3.3V Step-Down Converter
CMDSH-3
INPUT
5V
2.2μF
CERAMIC
OFF ON
0.18μF
BOOST
VIN VSW
LT1765-3.3
SHDN
FB
SYNC GND VC
2.2nF
1.5μH
UPS120
OUTPUT
3.3V
2.5A
4.7μF
CERAMIC
1765 TA01
Efficiency vs Load Current
90
VIN = 10V
VOUT = 5V
85
80
75
70
0
0.5 1.0 1.5
SWITCH CURRENT (A)
2.0
1765 • TAO1a
1765fd
1
1 page  
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage for
2.5V Out
3.5
3.3
3.1
2.9
2.7
2.5
0.001
0.01 0.1
LOAD CURRENT (A)
1
1765 G07
SHDN Supply Current
300
VIN = 15V
250
200
150
100
50
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
SHUTDOWN VOLTAGE (V)
1765 G08
Input Supply Current
1200
1000
800
UNDERVOLTAGE
LOCKOUT
600
400
200
0
0 5 10 15 20 25 30
INPUT VOLTAGE (V)
1765 G09
Maximum Load Current,
VOUT = 5V
3.0
2.8
L = 4.7μH
2.6
2.4 L = 2.2μH
2.2
2.0
0
L = 1.5μH
5 10 15 20
INPUT VOLTAGE (V)
25
1765 G11
Current Limit Foldback
4
40
3 30
SWITCH CURRENT
2 20
1 10
FB CURRENT
00
0 0.2 0.4 0.6 0.8 1 1.2
FEEDBACK VOLTAGE (V)
1765 G10
Maximum Load Current,
VOUT = 2.5V
3.0
L = 4.7μH
2.8
L = 2.2μH
2.6
L = 1.5μH
2.4
2.2
0
5 10 15 20
INPUT VOLTAGE (V)
25
1765 G12
1765fd
5
5 Page 
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
below the minimum VIN of 2.6V. This feature can be used
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
source defaults the open pin condition to be operating (see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
R1= VH − VL
7μA
R2
=
(
VH
−
1.33V
1.33V)
+
3μA
R1
VH – Turn-on threshold
VL – Turn-off threshold
Example: switching should not start until the input is above
4.75V and is to stop if the input falls below 3.75V.
VH = 4.75V
VL = 3.75V
R1= 4.75V − 3.75V = 143k
7μA
R2
=
(4.75V
1.33V
− 1.33V)
+
3μA
=
49.4k
143k
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high
resistor values are used, the SHDN pin should be bypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT1765 that may exceed its absolute maximum
LT1765
VIN SW
L1
5V
VIN C3
HIGH
FREQUENCY
CIRCULATING
PATH
D1 C1
LOAD
Figure 5. High Speed Switching Path
1765 F05
1765fd
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LT1765-1.8.PDF ] | |
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