PDF CDB4341A Data sheet ( Hoja de datos )

Número de pieza	CDB4341A
Descripción	24-Bit/ 192 kHz Stereo DAC with Volume Control
Fabricantes	Cirrus Logic
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No Preview Available ! CS4341A 24-Bit, 192 kHz Stereo DAC with Volume Control Features 101 dB Dynamic Range -91 dB THD+N +3.3 V or +5 V Power Supply 50 mW with 3. 3V supply Low Clock Jitter Sensitivity Filtered Line Level Outputs On-Chip Digital De-emphasis for 32, 44.1, and 48 kHz ATAPI Mixing Digital Volume Control with Soft Ramp – 94 dB Attenuation – 1 dB Step Size – Zero Crossing Click-Free Transitions Up to 200 kHz Sample Rates Automatic Mode Detection for Sample Rates between 4 and 2 0 0kHz Pin Compatible with the CS4341 Description The CS4341A is a complete stereo digital-to-analog sys- tem including digital interpolation, fourth-order delta- sigma digital-to-analog conversion, digital de-emphasis, volume control, channel mixing and analog filtering. The advantages of this architecture include: ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and tempera- ture and a high tolerance to clock jitter. The CS4341A accepts data at all standard audio sample rates up to 192 kHz, consumes very little power, oper- ates over a wide power supply range and is pin compatible with the CS4341, as described in section 3.1. These features are ideal for DVD audio players. ORDERING INFORMATION CS4341A-KS 16-pin SOIC, -10 to 70 °C CDB4341A Evaluation Board RST SCLK LRCK SDIN SC L/CCLK SDA/CDIN AD 0/C S MUTEC Control Port In te rfa c e External Mute Control Interpolation Filter Volume Control ∆Σ DAC Analog Filter AOUTA Mixer Interpolation Filter Volume Control ∆Σ DAC Analog Filter AOUTB ÷2 Preliminary Product Information Cirrus Logic, Inc. P.O. Box 17847, Austin, Texas 78760 http://www.cirrus.com MCLK This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2002 (All Rights Reserved) AUG ‘02 DS582PP1 1 1 page 1. PIN DESCRIPTION RST 1 1 6 MUTEC SDIN 2 1 5 AOUTA SCLK 3 1 4 VA LRCK 4 1 3 AGND MCLK 5 1 2 AOUTB SCL/CCLK 6 1 1 REF_GND SDA/CDIN 7 1 0 VQ AD0/CS 8 9 FILT+ CS4341A Pin Name RST SDIN SCLK LRCK MCLK SCL/CCLK SDA/CDIN AD0/CS FILT+ VQ REF_GND AOUTR AOUTL AGND VA MUTEC # Pin Description 1 Reset (Input) - Powers down device when enabled. 2 Serial Audio Data (Input) - Input for two’s complement serial audio data. 3 Serial Clock (Input) -Serial clock for the serial audio interface. 4 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. 5 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. 6 Serial Control Port Clock (Input) - Serial clock for the control port interface. 7 Serial Control Data I/O (Input/Output) - Input/Output for I2C data. Input for SPI data. 8 Address Bit / Chip Select (Input) - Chip address bit in I2C Mode. Control signal used to select the chip in SPI mode. 9 Positive Voltage Reference (Output) - Positive voltage reference for the internal sampling cir- cuits. 10 Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. 11 Reference Ground (Input) - Ground reference for the internal sampling circuits. 12 Analog Outputs (Output) - The full scale analog output level is specified in the Analog Charac- 15 teristics table. 13 Analog Ground (Input) - Ground reference. 14 Power (Input) - Positive power for the analog, digital, control port interface, and serial audio interface sections. 16 Mute Control (Output) - Control signal for optional mute circuit. DS582PP1 5 5 Page CS4341A 3.9 Control Port Interface The control port is used to load all the internal register settings (see section 5). The operation of the control port may be completely asynchronous with the audio sample rate. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port operates in one of two modes: I2C or SPI. Notes: MCLK must be applied during all I2C communication. 3.9.1 MAP Auto Increment The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I2C writes or reads, and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes of successive registers. 3.9.2 I2C Mode In the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial control port clock, SCL (see Figure 6 for the clock to data relationship). There is no CS pin. Pin AD0 enables the user to alter the chip address (001000[AD0][R/W]) and should be tied to VA or GND as required, before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after power-up, SPI mode will be selected. 3.9.2a I2C Write To write to the device, follow the procedure below while adhering to the control port Switching Specifications in section 7. 1) Initiate a START condition to the I2C bus followed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth bit of the address byte is the R/W bit. 2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This byte points to the register to be written. 3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to by the MAP. 4) If the INCR bit (see section 3.9.1) is set to 1, repeat the previous step until all the desired registers are written, then initiate a STOP condition to the bus. 5) If the INCR bit is set to 0 and further I2C writes to other registers are desired, it is nec- essary to initiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to other registers are desired, initiate a STOP condition to the bus. DS582PP1 11 11 Page

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