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PDF 74AHC2G00-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74AHC2G00-Q100 | |
| Descripción | Dual 2-input NAND gate | |
| Fabricantes | NXP Semiconductors | |
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74AHC2G00-Q100;
74AHCT2G00-Q100
Dual 2-input NAND gate
Rev. 1 — 21 March 2013
Product data sheet
1. General description
The 74AHC2G00-Q100; 74AHCT2G00-Q100 are high-speed Si-gate CMOS devices.
They provide two 2-input NAND gates.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Symmetrical output impedance
High noise immunity
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Low power dissipation
Balanced propagation delays
Multiple package options
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G00DP-Q100 40 C to +125 C TSSOP8
74AHCT2G00DP-Q100
74AHC2G00DC-Q100 40 C to +125 C VSSOP8
74AHCT2G00DC-Q100
Description
Version
plastic thin shrink small outline package; 8 leads; SOT505-2
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
SOT765-1
1 page  
NXP Semiconductors
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
Table 7. Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
VOH
HIGH-level VI = VIH or VIL
output voltage IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
VOL LOW-level VI = VIH or VIL
output voltage IO = 50 A; VCC = 2.0 V
IO = 50 A; VCC = 3.0 V
IO = 50 A; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
II input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
CI input
capacitance
74AHCT2G00-Q100
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
VOH
VOL
II
ICC
ICC
CI
HIGH-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage IO = 50 A
IO = 8.0 mA
input leakage VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
additional
per input pin; VI = 3.4 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
input
capacitance
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min
Max
1.9 2.0 -
1.9
-
1.9
-V
2.9 3.0 -
2.9
-
2.9
-V
4.4 4.5 -
4.4
-
4.4
-V
2.58 -
- 2.48
-
2.40
-V
3.94 - - 3.8 - 3.70 - V
- 0 0.1 -
0.1
-
0.1 V
- 0 0.1 -
0.1
-
0.1 V
- 0 0.1 -
0.1
-
0.1 V
- - 0.36 - 0.44 -
0.55 V
- - 0.36 - 0.44 -
0.55 V
- - 0.1 -
1.0
-
2.0 A
- - 10 -
10
-
40 A
- 1.5 10
-
10
-
10 pF
2.0 - - 2.0 - 2.0
-V
- - 0.8 -
0.8
-
0.8 V
4.4 4.5 -
4.4
-
4.4
-V
3.94 - - 3.8 - 3.70 - V
- 0 0.1 -
0.1
-
- - 0.36 - 0.44 -
- - 0.1 -
1.0
-
- - 1.0 -
10
-
- - 1.35 - 1.5 -
0.1 V
0.55 V
2.0 A
40 A
1.5 mA
- 1.5 10
-
10
-
10 pF
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
74AHC2G00-Q100; 74AHCT2G00-Q100
Dual 2-input NAND gate
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
MIL Military
15. Revision history
Table 12. Revision history
Document ID
Release date
74AHC_AHCT2G00_Q100 v.1 20130321
Data sheet status
Product data sheet
Change notice Supersedes
--
74AHC_AHCT2G00_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 21 March 2013
© NXP B.V. 2013. All rights reserved.
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