PDF ADRF6720-27 Data sheet ( Hoja de datos )

Número de pieza	ADRF6720-27
Descripción	Wideband Quadrature Modulator
Fabricantes	Analog Devices
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Data Sheet Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs ADRF6720-27 FEATURES I/Q modulator with integrated fractional-N PLL RF output frequency range: 400 MHz to 3000 MHz Internal LO frequency range: 356.25 MHz to 2855 MHz Output P1dB: 10.8 dBm at 2140 MHz Output IP3: 31.1 dBm at 2140 MHz Carrier feedthrough: −44.3 dBm at 2140 MHz Sideband suppression: −40.8 dBc at 2140 MHz Noise floor: −159.5 dBm/Hz at 2140 MHz Baseband 1 dB modulation bandwidth: >1000 MHz Baseband input bias level: 2.68 V Power supply: 3.3 V/425 mA Integrated RF tunable balun allowing single-ended RF output Multicore integrated VCOs HD3/IP3 optimization Sideband suppression and carrier feedthrough optimization High-side/low-side LO injection Programmable via 3-wire serial port interface (SPI) 40-lead 6 mm × 6 mm LFCSP APPLICATIONS 2G/3G/4G/LTE broadband communication systems Microwave point-to-point radios Satellite modems Military/aerospace Instrumentation GENERAL DESCRIPTION The ADRF6720-27 is a wideband quadrature modulator with an integrated synthesizer ideally suited for 3G and 4G com- munication systems. The ADRF6720-27 consists of a high linearity broadband modulator, an integrated fractional-N phase-locked loop (PLL), and four low phase noise multicore voltage controlled oscillators (VCOs). The ADRF6720-27 local oscillator (LO) signal can be generated internally via the on-chip integer-N and fractional-N synthesizers, or externally via a high frequency, low phase noise LO signal. The internal integrated synthesizer enables LO coverage from 356.25 MHz to 2855 MHz using the multicore VCOs. In the case of internal LO generation or external LO input, quadrature signals are generated with a divide by 2 phase splitter. When the ADRF6720-27 is operated with an external 1 × LO input, a polyphase filter generates the quadrature inputs to the mixer. The ADRF6720-27 offers digital programmability for carrier feedthrough optimization, sideband suppression, HD3/IP3 optimization, and high-side or low-side LO injection. The ADRF6720-27 is fabricated using an advanced silicon- germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP package with an exposed pad. Performance is specified over the −40°C to +85°C temperature range. FUNCTIONAL BLOCK DIAGRAM VPOSx I+ 3 I– 4 40 35 30 V TO I LO NULLING DAC 26 22 17 11 PHASE CORRECTION 6 ADRF6720-27 27 ENBL 24 RFOUT Q– 8 Q+ 9 REFIN 39 CP 36 VTUNE 32 LO NULLING DAC V TO I PLL QUAD DIVIDER LOIN– 33 LOIN+ 34 POLYPHASE FILTER 2 5 7 10 16 20 23 25 29 37 38 GND PHASE CORRECTION 18 LOOUT+ 19 LOOUT– LDO 2.5V LDO VCO 12 28 DECL1 DECL2 SERIAL PORT INTERFACE 31 DECL3 15 CS 14 SCLK 13 SDIO Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page ADRF6720-27 Parameter Output IP2 Output IP3 Noise Floor RF OUTPUT = 2140 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RF OUTPUT = 2300 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RF OUTPUT = 2600 MHz Output Power, POUT Modulator Voltage Gain Output P1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Data Sheet Test Conditions/Comments f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier offset I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz carrier offset Baseband VIQ = 1 V p-p differential Min POUT − P(fLO ± (2 × fBB)) POUT − P(fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier offset I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz carrier offset Baseband VIQ = 1 V p-p differential POUT − P(fLO ± (2 × fBB)) POUT − P(fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential I/Q input with 2.68 V dc bias and no RF output, 20 MHz carrier offset I/Q input with 2.68 V dc bias and −10 dBm RF output, 20 MHz carrier offset Baseband VIQ = 1 V p-p differential POUT − P(fLO ± (2 × fBB)) POUT − P(fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, baseband I/Q amplitude per tone = 0.3 V p-p differential Rev. B \| Page 4 of 43 Typ Max Unit 59.8 dBm 32.7 dBm −157.5 dBm/Hz −156.6 dBm/Hz 4.0 0.02 10.8 −44.3 −40.8 −0.78 −0.015 −58.4 −67.3 58.7 31.1 −159.5 −158.6 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm/Hz 3.5 −0.48 10.3 −40.8 −37.4 −1.38 −0.015 −58.8 −65.8 57.5 28.1 −158.6 −157.5 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz dBm/Hz 2.9 −1.08 9.9 −37.1 −40.7 −0.80 0.003 −61.2 −59.1 53.5 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm 5 Page ADRF6720-27 Data Sheet Pin No. 36 37 38 39 40 Mnemonic CP GND GND REFIN VPOS8 EP Description Charge Pump Output. Charge Pump Ground. PLL Reference Ground. PLL Reference Input. 3.3 V Supply Voltage for PLL Reference. Decouple VPOS8 with 100 pF and 0.1 µF capacitors located close to the pin. Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. B \| Page 10 of 43 11 Page

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