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PDF HV7321 Data sheet ( Hoja de datos )
| Número de pieza | HV7321 | |
| Descripción | High-Voltage Ultrasound Pulser | |
| Fabricantes | Microchip | |
| Logotipo |  |
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HV7321
4-Ch. 5-Level ±80V High-Voltage Ultrasound Pulser with T/R Switches
Features
• Power Sequencing Free 5 Output Levels
including RTZ (Return-to-Zero)
• -44 dB Single-Cycle Pulse-Inversion Second
Harmonic Distortion (HD2) at 5 MHz
• Output Voltage up to ±80V
• ±2.5A Peak Output Current
• ±300 mA Current from VPP1/VNN1 in CW Mode-0
• Integrated T/R Switch & RX Damper Switch
• Bleeder Switches Achieve True Zero during RTZ
• Supports Both Transparent and Re-Timing Mode
• Re-Timing Clock Frequency Supports up to
220 MHz
• Built-In Output Protection Diodes and Clamp
Diodes
• +2.5/+3.3V Input Logic
• Built-In CW Switches to Pair with External CW
Transmitters (CW Mode-1)
• 9 mm x 9 mm 64-Lead VQFN Package
Applications
• Medical Ultrasound Imaging Systems
• NDT Ultrasound
• Piezoelectric or Capacitive Transducer Drivers
General Description
The HV7321 is a 4-channel, 5-level, ultrasound
transmitter with built-in T/R switches, output protection
diodes and clamp diodes. The HV7321 can provide up
to ±2.5A and the output voltage swing can be up to
±80V. The HV7321 supports both Transparent and
Re-Timing mode. The re-timing clock frequency can
support up to 220 MHz. The re-timing feature helps
reduce the output jitter introduced by the driving the
field-programmable gate array (FPGA).
The HV7321 has two different modes for
CW transmission, CW-Mode 0 and CW-Mode 1.
In CW-Mode 0 (Mode = 0, PWS = 0), the VPP1 and
VNN1 rails are used for CW transmission. The output
current is reduced in CW Mode-0.
In CW-Mode 1, the HV7321 accepts the output of an
external CW beamformer as CW source.
The HV7321 is LVCMOS 2.5V/3.3V input compatible,
which can be interfaced with the FPGA directly.
The HV7321 is available in a 9 mm x 9 mm 64-Lead
VQFN package.
2016 Microchip Technology Inc.
DS20005639A-page 1
1 page  
HV7321
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Positive logic supply (VLL).......................................................................................................................... -0.5V to +5.5V
All I/O & CLK pin voltage (VIO)................................................................................................................... -0.5V to +5.5V
Positive voltage supply (VDD)..................................................................................................................... -0.5V to +5.5V
Positive gate driver supply (VGP) ............................................................................................................. -0.5V to +13.5V
Negative gate driver supply (VGN) ........................................................................................................... -13.5V to +0.5V
High voltage positive supply (VPP0,1) .......................................................................................................... -1.0V to +85V
High voltage negative supply (VNN0,1,2)...................................................................................................... -85V to +1.0V
CW input voltage (VCWIN) .......................................................................................................................... -7.5V to +7.5V
TX pin voltage (VTX)..................................................................................................................................... -85V to +85V
RX pin to GND voltage (VRX) ....................................................................................................................... ±0.7 to ±1.4V
Operating temperature ................................................................................................................................ 0°C to +85°C
Storage temperature ............................................................................................................................... -55°C to +150°C
Maximum junction temperature............................................................................................................................ +130°C
Maximum not-latch-up current ........................................................................................................................... +100 mA
ESD Rating CWIN,TX, VPP, VNN pins ......................................................................................................................±500V
ESD Rating – all other pins ....................................................................................................................................... ±2kV
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical specifications: VLL = +2.5V, VDD = +5.0V, VPP0,1 = +80V, VNN0,1,2 = -80V, VGP = +10V, VGN = -10V,
VSUB = 0V, PWS = OEN = REN = 1, TA = 25°C, unless otherwise specified. Parameters in Bold apply over the
operating temperature range of TA = TJ = 0 to +85°C.
Parameter
Sym. Min. Typ. Max. Unit
Conditions
Operating Supply Voltages
Positive Logic Supply
Positive Voltage Supply
Positive Gate Driver Supply
Negative Gate Driver Supply
High Voltage Positive Supply
High Voltage Negative Supply
VLL
VDD
VGP
VGN
VPP0
VPP1
VNN0
VNN1
2.25 2.50
4.75 5.0
8.0 10
-12 -10
0—
0—
-80 —
-80 —
Operating Supply Current
VLL Quiescent Current
ILLQ — 0.06
VDD Quiescent Current
IDDQ
— 30
VPP0 Quiescent Current
IPP0Q
— 0.37
VNN0 Quiescent Current
INN0Q
-9 -0.78
VPP1 Quiescent Current
IPP1Q
— 0.44
VNN1 Quiescent Current
INN1Q
-10 -1.46
VNN2 Quiescent Current
INN2Q
-7 -3.84
Note 1: Characterized only; not 100% tested in production.
2: Design guidance only.
3.60
5.25
12
-8.0
80
80
0
0
0.7
80
6
—
10
—
—
V Note 1
V Note 1
V
Note 1
See Table 3-1.
V
Note 1
Must be VPP0 ≥ VPP1
V
Note 1
Must be VNN0 VNN1
μA
µA
µA
µA OEN = REN = 0
µA
µA
µA
2016 Microchip Technology Inc.
DS20005639A-page 5
5 Page 
HV7321
TABLE 1-1: INPUT OUTPUT LOGIC TRUTH TABLE (TRANSPARENT, CLK = 0)
Function
Pulsed-Echo
Mode (1)
OTPN
OEN MODE
Logic Inputs
PWS CLK SEL
11
0
1
0
0
11
0
1
0
0
11
0
1
0
0
11
0
1
0
0
11
0
1
0
1
11
0
1
0
1
11
0
1
0
1
11
0
1
0
1
11
0
0
0
0
NEG
0
0
1
1
0
0
1
1
0
POS
0
1
0
1
0
1
0
1
0
TX
Output
RTZ
VPP0
VNN0
RTZ+(4)
RTZ
VPP1
VNN1
high Z
RTZ
RTZSW
&
TRSW
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
CWSW RXDMP
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
ON
CW Mode-0 (2)
1
1
1
1
1
1
1
1
0
0
0
0
0 0 0 0 1 VPP0 OFF
0 0 0 1 0 VNN0 OFF
0
0
0
1
1 RTZ+(4)
ON
0 0 1 0 0 RTZ OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
11
11
11
CW Mode-1 (3) 1
1
0
0
0
1
0 0 1 0 1 VPP1 OFF
0 0 1 1 0 VNN1 OFF
0 0 1 1 1 high Z OFF
other than 011
high Z
OFF
xx
0
1
1 RTZ+(4)
ON
OFF
OFF
OFF
ON
OFF
ON
ON
ON
ON
OFF
Device
Disabled
x0
x
x x x x x high Z OFF
OFF
ON
Thermal
Protection
Activated
0x
x
x x x x x high Z OFF
OFF
ON
Note 1:
2:
3:
4:
In Pulsed-Echo mode, low duty cycle must be used due to the IC power dissipation limit.
When PWS = 0, VPP1/VNN1 output current is reduced for low-voltage CW mode-0. VPP0/VNN0 output current is
unaffected when PWS = 1, as in Pulsed-Echo mode.
In CW MODE = 1, the CWSW is turned on to use external CW waveform at CWIN, if the channel
SEL = NEG = POS = 0.
When SEL = 0, NEG = 1, POS = 1, the channel is in Receiving mode (RTZ+).
2016 Microchip Technology Inc.
DS20005639A-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HV7321.PDF ] | |
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