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PDF A8653 Data sheet ( Hoja de datos )
| Número de pieza | A8653 | |
| Descripción | Synchronous USB Buck Regulator | |
| Fabricantes | Allegro | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de A8653 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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A8652, A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
FEATURES AND BENEFITS
• Automotive AEC-Q100 qualified
• Cable and wiring drop compensation
• Dynamic voltage correction with controller
• Integrated high-side and low-side switching MOSFETs
• Programmable load-side current limit
• Maximized duty cycle for low dropout operation
• Operating input voltage range: 4 V to 36 V
• UVLO STOP threshold is at 2.6 VTYP
• Withstands surge voltages up to 40 V
• Continuous loading: 2.6 A for A8653; 1 A for A8652
• Adjustable switching frequency (fSW): 100 kHz to
2.2 MHz
• Synchronization to external clock: 100 kHz to 2.2 MHz
• Frequency dithering for lower EMI signature
• External adjustable compensation network
• Stable with ceramic output capacitors
Continued on next page...
PACKAGES:
16-Pin eTSSOP (suffix LP) with exposed thermal pad
Not to scale
DESCRIPTION
The A8652/53 is a high output current synchronous buck
regulator that provides tight load regulation over a wiring
harness without the need for remote sense lines.This remote load
regulation is achieved with an integrated open-loop correction
scheme that, given a known wiring harness resistance, adjusts
the output voltage based on the measured load current and a
user-programmable gain, achieving ±2% accuracy at 500 mV
of correction. The Remote Load Regulation control includes a
115% regulated voltage clamp in conjunction with a dynamic
overvoltage protection, with OVP threshold changing with the
correction voltage. TheA8652/53 includes a user-configurable
load-side current limit to fold back the output voltage during an
output overcurrent condition. TheA8652/53 regulates nominal
input voltages from 4 to 36 V and remains operational when
VIN drops as low as 2.6 V. When the input voltage approaches
the output voltage, the duty cycle is maximized to maintain
the output voltage.
The A8652/53 features include externally set soft-start time,
external compensation network, an EN input to enable VOUT,
a SYNC/FSET input to synchronize or set the PWM switching
APPLICATIONS
• Automotive USB Power Ports
• Rear Seat Entertainment
• Navigation Systems
• Motorcycle Clusters
Continued on next page...
VIN
CIN
VIN
2 × 4.7 µF
GND
EN
RFSET
SYNC/FSET
CSS
22 nF
SS
RZ
CP
CZ
COMP
FB
A8652/3
BOOT
SW
GADJ
CBOOT
100 nF
RGADJ
LO
CO
RSEN
VOUT
ISEN+
ISEN-
IADJ
CF
(optional)
RF
(optional)
RIADJ
POK
RPU
10 kΩ
RFB1
24.9 kΩ
RFB2
4.75 kΩ
RWIRE/2
RWIRE/2
VLOAD
CLOAD
A8652/53-DS, Rev.2
Typical Application Diagram 1
1 page  
A8652,
A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
VIN
EN
500 nA
SYNC/FSET
FB
COMP
400 mV
SS
POK
Regulator
VREF
VREG
TSD
OSC
Adj
80 mV
Error Amp
5 µs
Slope
Comp
UV
OV
VIN BOOT REG
UVLO
OCP
Current Sense
Amp
Isen
EN
OVP
Protection & Fault
BOOT
SW
CLK
PWM
COMP
Σ
Ramp
Offset
2 kΩ
FAULT
920 mV
PWM
Control VREG
Logic
80 mΩ
55 mΩ
PGND
HICCUP
LOGIC
20 µA 5 µA
REF_ADJ
VREF
800 mV
Sense
Amp
Adj
ISEN+
ISEN–
GADJ
SGND
IADJ
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
5 Page 
A8652,
A8653
Wide Input Voltage, Synchronous USB Buck Regulator
with Remote Load Regulation
6.00
5.95
5.90
5.85
5.80
5.75
5.70
5.65
5.60
5.55
5.50
-50 -25 0 25 50 75 100 125 150 175
Temperature (ºC)
ISEN+ Overvoltage Thresholds versus Temperature
(test with VGADJ = 0 V)
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
2.5
V
OUT
V
LOAD
3.0 3.5 4.0 4.5 5.0 5.5
V (V)
IN
Low VIN Dropout Operation at 5 Ω Load
6.0
2.5
5.5
5.0
4.5
4.0
3.5
3.0
-50 -25
0
25
50
75
100 125
150
Temperature (ºC)
Quiescent Current IQ versus Temperature
175
96
94
92
90
88
86
84
82
80
78
0
VIN = 8 V
VIN = 12 V
VIN = 16 V
0.5 1.0 1.5 2.0 2.5 3.0
Load (A)
Efficiency versus Output Current
(Typical Design A in Table 3)
5.2 V
5.1 V
5.0 V
4.9 V
V
OUT
V
LOAD
5.2 V
5.1 V
5.0 V
4.9 V
V
OUT
V
LOAD
25 mA/µs
1 A/div
C4
I
OUT
C2 100 µs/div
Transient Response 0 to 1 A Load Step
(Typical Design A in Table 3)
1 A/div
I
OUT
25 mA/µs
100 µs/div
Transient Response 1 to 2 A Load Step
(Typical Design A in Table 3)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A8653.PDF ] | |
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