AT45DB642D Datasheet PDF - Adesto
| Part Number | AT45DB642D | |
| Description | 64-megabit 2.7V Dual-interface DataFlash | |
| Manufacturers | Adesto | |
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Features
• Single 2.7V - 3.6V Supply
• Dual-interface Architecture
– RapidS Serial Interface: 66MHz Maximum Clock Frequency
SPI Compatible Modes 0 and 3
– Rapid8 8-bit Interface: 50MHz Maximum Clock Frequency
• User Configurable Page Size
– 1024-Bytes per Page
– 1056-Bytes per Page
– Page Size Can Be Factory Pre-configured for 1024-Bytes
• Page Program Operation
– Intelligent Programming Operation
– 8192 Pages (1024-/1056-Bytes/Page) Main Memory
• Flexible Erase Options
– Page Erase (1-Kbyte)
– Block Erase (8-Kbytes)
– Sector Erase (256-Kbytes)
– Chip Erase (64Mbits)
• Two SRAM Data Buffers (1024-/1056-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
• Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
• Low-power Dissipation
– 10mA Active Read Current Typical – Serial Interface
– 10mA Active Read Current Typical – 8-bit Interface
– 25µA Standby Current Typical
– 15µA Deep Power Down Typical
• Hardware and Software Data Protection Features
– Individual Sector
• Permanent Sector Lockdown for Secure Code and Data Storage
– Individual Sector
• Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
• JEDEC Standard Manufacturer and Device ID Read
• 100,000 Program/Erase Cycles Per Page Minimum
• Data Retention – 20 Years
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
• Temperature Range
– Industrial: -40C to +85C
64-megabit
2.7V Dual-interface
DataFlash
AT45DB642D
(Not Recommended
for New Designs)
3542N–DFLASH–2/2014
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3. Block Diagram
AT45DB642D
WP FLASH MEMORY ARRAY
PAGE (1024-/1056-BYTES)
BUFFER 1 (1024-/1056-BYTES)
BUFFER 2 (1024-/1056-BYTES)
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
I/O INTERFACE
SI SO
I/O7 - I/O0
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB642D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page by page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
8192/8,448 bytes
SECTOR 0b = 248 Pages
253,952/261,888 bytes
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
SECTOR 1 = 256 Pages
262,144/270,336 bytes
SECTOR 2 = 256 Pages
262,144/270,336 bytes
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
SECTOR 30 = 256 Pages
262,144/270,336 bytes
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 31 = 256 Pages
262,144/270,336 bytes
BLOCK 1022
BLOCK 1023
Block = 8,192-/8,448-bytes
PAGE 8,190
PAGE 8,190
Page = 1,024-/1,056-bytes
3542N–DFLASH–2/2014
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AT45DB642D electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AT45DB642D.PDF Datasheet ] | |
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| Part Number | Description | MFRS |
| AT45DB642 | The function is 64-megabit 2.7-volt Only Dual-interface DataFlash. ATMEL Corporation |  |
| AT45DB642D | The function is 64-megabit 2.7V Dual-interface DataFlash. Adesto | |
| AT45DB642D | The function is 64-megabit 2.7-volt Dual-interface DataFlash. ATMEL Corporation | |
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