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PDF 8SLVD1204-33 Data sheet ( Hoja de datos )
| Número de pieza | 8SLVD1204-33 | |
| Descripción | LVDS Output Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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2:4, LVDS Output Fanout Buffer
8SLVD1204-33
DATA SHEET
General Description
The 8SLVD1204-33 is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The 8SLVD1204-33
is characterized to operate from a 3.3V power supply. Guaranteed
output-to-output and part-to-part skew characteristics make the
8SLVD1204-33 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
selectable differential inputs and four low skew outputs are available.
The integrated bias voltage reference enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLKx, nPCLKx pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 310ps (maximum)
• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
10kHz - 20MHz: 100fs (maximum)
• Full 3.3V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
VDD
PCLK0
nPCLK0
Pulldown
Pullup/Pulldown
GND GND
VDD
PCLK1
nPCLK1
Pulldown
Pullup/Pulldown
GND GND
VDD
SEL Pullup/Pulldown
VREF
GND
Reference
Voltage
Generator
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Pin Assignment
12 11 10
Q2 13
9
8 VREF
nQ2 14
Q3 15
8SLVD1204-33
8XXXXXX
7 nPCLK0
6 PCLK0
nQ3 16
5 VDD
12 3 4
16-pin, 3mm x 3mm VFQFN Package
8SLVD1204-33 REVSION B 03/11/15
1 ©2015 Integrated Device Technology, Inc.
1 page  
8SLVD1204-33 DATA SHEET
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VDD = 3.3V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fREF
Input
PCLK[0:1],
Frequency nPCLK[0:1]
2 GHz
V/t
Input
PCLK[0:1],
Edge Rate nPCLK[0:1]
1.5 V/ns
tPD
tsk(o)
Propagation Delay;
NOTE 1
Output Skew;
NOTES 2, 3
PCLK[0:1], nPCLK[0:1] to any Qx, nQx
for VPP = 0.1V or 0.3V
120 215
310 ps
20 ps
tsk(i)
Input Skew; NOTE 3
20 ps
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew;
NOTES 3, 4
fREF = 100MHz
15 ps
230 ps
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 1kHz – 40MHz
139 190 fs
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
95 140 fs
fREF = 122.88MHz Square Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
95 140 fs
Buffer Additive Phase
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 1kHz – 40MHz
tJIT
Jitter, RMS; refer to
Additive Phase Jitter
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 10kHz – 20MHz
Section
fREF = 156.25MHz Square Wave, VPP = 1V,
Integration Range: 12kHz – 20MHz
90 130 fs
67 100 fs
67 100 fs
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 1kHz – 40MHz
94 140 fs
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 10kHz – 20MHz
70 105 fs
fREF = 156.25MHz Square Wave, VPP = 0.5V,
Integration Range: 12kHz – 20MHz
70 105 fs
tR / tF
Output Rise/ Fall Time
20% to 80%
outputs loaded with 100
40
250 ps
MUXISOLATION Mux Isolation; NOTE 5
fREF = 100MHz
74 dB
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
NOTE 5: Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
REVSION B 03/11/15
5 2:4, LVDS OUTPUT FANOUT BUFFER
5 Page 
8SLVD1204-33 DATA SHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any
transmission-line reflection issues, the components should be
surface mounted and must be placed as close to the receiver as
possible. IDT offers a full line of LVDS compliant devices with two
types of output structures: current source and voltage source. The
standard termination schematic as shown in Figure 3A can be used
with either type of output structure. Figure 3B, which can also be
used with both output types, is an optional termination with center tap
capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it
is recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
ZO ZT
Figure 3A. Standard Termination
LVDS
ZT Receiver
LVDS
Driver
ZO ZT
Figure 3B. Optional Termination
LVDS Termination
ZT
2 LVDS
C ZT Receiver
2
REVSION B 03/11/15
11 2:4, LVDS OUTPUT FANOUT BUFFER
11 Page | ||
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