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PDF 9DBV0641 Data sheet ( Hoja de datos )
| Número de pieza | 9DBV0641 | |
| Descripción | 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB | |
| Fabricantes | IDT | |
| Logotipo |  |
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6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBV0641
DATASHEET
Description
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
• 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF phase jitter is PCIe Gen1-2-3 compliant
• DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
• Direct connection to 100ohm transmission lines; saves 24
resistors compared to standard PCIe devices
• 55mW typical power consumption in PLL mode; minimal
power consumption
• Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 40-pin 5x5mm VFQFPN; minimal board
space
• 3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0641 REVISION B 09/11/14 1 ©2014 Integrated Device Technology, Inc.
1 page  
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs Zo=100W
Rs
Device
2pF 2pF
Driving LVDS
Driving LVDS
Rs
Device
Rs
Cc
Cc
3.3V
R7a
Zo
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
9DBV0641 DATASHEET
REVISION B 09/11/14
5 6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
5 Page 
9DBV0641 DATASHEET
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
T starT bit
Slave Address
WR WRite
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
O
O
O
Byte N + X - 1
P stoP bit
ACK
ACK
ACK
ACK
O
O
O
ACK
Note: Read/Write address is latched on SADR pin.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T starT bit
Slave Address
WR WRite
Beginning Byte = N
RT Repeat starT
Slave Address
RD ReaD
IDT
ACK
ACK
ACK
ACK
ACK
O
O
O
N Not acknowledge
P stoP bit
Data Byte Count=X
Beginning Byte N
O
O
O
Byte N + X - 1
REVISION B 09/11/14
11 6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet 9DBV0641.PDF ] | |
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