PDF ADF4356 Data sheet ( Hoja de datos )

Número de pieza	ADF4356
Descripción	6.8 GHz Wideband Synthesizer
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de ADF4356 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! Data Sheet 6.8 GHz Wideband Synthesizer with Integrated VCO ADF4356 FEATURES GENERAL DESCRIPTION RF output frequency range: 53.125 MHz to 6800 MHz Integer channel: −227 dBc/Hz Fractional channel: −225 dBc/Hz Integrated RMS jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output Fractional-N synthesizer and integer-N synthesizer Pin compatible to the ADF4355 High resolution, 52-bit modulus Phase frequency detector (PFD) operation to 125 MHz Reference input frequency operation to 600 MHz Maintains frequency lock over −40°C to +85°C Low phase noise, voltage controlled oscillator (VCO) Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output Analog and digital power supplies: 3.3 V Charge pump and VCO power supplies: 5.0 V typical Logic compatibility: 1.8 V Programmable output power level RF output mute function Supported in the ADIsimPLL design tool The ADF4356 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz. The ADF4356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. Control of all on-chip registers is through a simple 3-wire interface. The ADF4356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF4356 also contains hardware and software power-down modes. APPLICATIONS Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS) Point to point/point to multipoint microwave links Satellites/VSATs Test equipment/instrumentation Clock generation FUNCTIONAL BLOCK DIAGRAM CE DVDD AVDD DVDD VP VVCO VRF REFINA REFINB CLK DATA LE ×2 DOUBLER 10-BIT R COUNTER ÷2 DIVIDER DATA REGISTER FUNCTION LATCH INTEGER FRACTION MODULUS VALUE VALUE VALUE THIRD-ORDER FRACTIONAL INTERPOLATOR N COUNTER LOCK DETECT MULTIPLEXER CHARGE PUMP PHASE COMPARATOR VCO CORE ÷1/2/4/8/16/ 32/64 MUXOUT CREG1 CREG2 CPOUT OUTPUT STAGE OUTPUT STAGE VTUNE VREF VBIAS VREGVCO RFOUTA+ RFOUTA– PDBRF RFOUTB+ RFOUTB– MULTIPLEXER ADF4356 AGND SDGND CPGND Figure 1. AGNDRF AGNDVCO Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet ADF4356 Parameter Normalized In-Band Phase Noise Floor Fractional Channel5 Integer Channel6 Normalized 1/f Noise, PN1_f7 Integrated RMS Jitter (1 kHz to 20 MHz)8 Spurious Signals Due to PFD Frequency Symbol Min Typ Max −225 −227 −121 97 −85 Unit Test Conditions/Comments dBc/Hz dBc/Hz dBc/Hz fs dBc 10 kHz offset; normalized to 1 GHz 1 VCP is the voltage at the CPOUT pin. 2 IOL is the output low current. 3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz. 4 RF output power using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. Unused RF output pins are terminated in 50 Ω. 5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −225 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel. 6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula: −227 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the ADIsimPLL design tool. 8 Integrated RMS jitter using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. The EV-ADF4356SD1Z evaluation board is configured to accept a single ended REFIN (SMA 100) = 160 MHz, VCO frequency = 6 GHz, PFD frequency = 80 MHz, charge pump current = 0.9 mA, and bleed current is off. The loop filter is configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated in 50 Ω. TIMING CHARACTERISTICS AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Write Timing Parameter Limit fCLK 50 t1 10 t2 5 t3 5 t4 10 t5 10 t6 10 t7 20 or (2/fPFD), whichever is longer Unit MHz max ns min ns min ns min ns min ns min ns min ns min Description Serial peripheral interface CLK frequency LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width Write Timing Diagram CLK t4 t5 DATA DB31 (MSB) LE t1 t2 t3 DB30 DB3 (CONTROL BIT C4) DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 Figure 2. Write Timing Diagram t6 Rev. 0 \| Page 5 of 35 5 Page Data Sheet –60 –80 –100 –120 –140 –160 –180 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 16. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ = 1550.2 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4 Selected, Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz –60 –80 –100 –120 –140 –160 –180 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 17. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ = 2113.5 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2 Selected, Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz ADF4356 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 18. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2 Selected, Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz 4650 4600 4550 4500 4450 4400 1 4350 4300 4250 4200 4150 –1 0 1 2 3 4 TIME (ms) Figure 19. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz, Loop Bandwidth = 23 kHz Rev. 0 \| Page 11 of 35 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet ADF4356.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ADF4350	Wideband Synthesizer	Analog Devices
ADF4351	Wideband Synthesizer	Analog Devices
ADF4355	Microwave Wideband Synthesizer	Analog Devices
ADF4355-2	Microwave Wideband Synthesizer	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar