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844S42I Datasheet دیتاشیت PDF دانلود

دیتاشیت - IDT - Dual Output RF Frequency Synthesizer

شماره قطعه 844S42I
شرح مفصل Dual Output RF Frequency Synthesizer
تولید کننده IDT 
آرم IDT 


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844S42I شرح
Dual Output RF Frequency Synthesizer
844S42I
Data Sheet
General Description
The 844S42I is a 3.3V compatible, PLL based clock synthesizer
targeted for clock generation in high-performance instrumentation,
networking and computing applications. Using either the serial (I2C)
or parallel programming interface, the 844S42I enables the
generation of clock frequencies in the range of 81MHz to 2592MHz.
The internal crystal oscillator uses the external quartz crystal as the
basis of its frequency reference. Alternatively, a LVCMOS compatible
clock signal can be used as PLL reference signal. The devices uses
an integer-N synthesizer architecture and is optimized for low-jitter
generation. The VCO within the PLL operates over a range of
1296MHz to 2592MHz. Its output is scaled by a divider that is
configured by either the I2C or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL pre-divider P, the feedback-divider
M and the PLL post-divider N determine the output frequency. The
feedback path of the PLL is internal.
The PLL post-dividers NA and NB are configured through either the
I2C or the parallel interfaces, each can provide one of seven division
ratios (1, 2, 3, 4, 6, 8, 16). This divider extends the performance of
the part while providing a typical 50% duty cycle. The high-frequency
outputs QA and QB are differential and are capable of driving a pair
of transmission lines. The positive supply voltage for the internal PLL
is separated from the power supply for the core logic and output
drivers to minimize noise induced jitter. The serial interface is I2C
compatible and provides read and write access to the internal PLL
configuration registers. The lock state of the PLL is indicated by the
LVCMOS-compatible LOCK_DT output. The 844S42I is packaged
in a 8mm x 8mm 56-lead VFQFN package.
Features
Programmable frequency synthesis optimized for instrumentation,
networking and computing applications
81MHz to 2592MHz synthesized clock output signal
Two differential, universal LVDS or LVPECL compatible
high-frequency outputs
Output frequency programmable through 2-wire I2C bus or
parallel interface
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS/LVTTL compatible reference clock input
Clock stop and output enable functionality
PLL lock indicator output (LVCMOS/LVTTL)
LVCMOS/LVTTL compatible control inputs
Fully integrated PLL
SiGe Technology
Full 3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in a lead-free (RoHS 6) compliant package
Pin Assignment
GND
nc
nBYPASS
nc
VDD
REF_CLK
GND
REF_SEL
XTAL_IN
XTAL_OUT
nMR
LOCK_DT
LEV_SEL
VDD
56 55 54 53 52 51 50 49 48 47 46 45 44 43
1 42
2 41
3 40
4 39
5 ICS844S42I 38
6 56-Lead VFQFN
7 8mm x 8mm x 0.925mm
8
9
package body
10 K Package
11 Top View
37
36
35
34
33
32
12 31
13 30
14 29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
nc
VDDOA
VDDOA
QA
nQA
GND
GND
GND
GND
QB
nQB
VDDOB
VDDOB
nc
©2016 Integrated Device Technology, Inc
1
Revision A April 28, 2016

قانون اساسیصفحه 28
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