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PDF CD4013BMS Data sheet ( Hoja de datos )

Número de pieza CD4013BMS
Descripción CMOS Dual D-Type Flip-Flop
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! CD4013BMS Hoja de datos, Descripción, Manual

CD4013BMS
December 1992
CMOS Dual ‘D’-Type Flip-Flop
Features
Pinout
• High-Voltage Type (20V Rating)
• Set-Reset Capability
• Static Flip-Flop Operation - Retains State Indefinitely
With Clock Level Either “High” Or “Low”
• Medium-Speed Operation - 16 MHz (typ.) Clock Toggle
Rate at 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Registers
• Counters
• Control Circuits
Q1 1
Q1 2
CLOCK 1 3
RESET 1 4
D1 5
SET 1 6
VSS 7
Functional Diagram
6
SET 1
D1
CLOCK 1
5
3
4
RESET 1
8
SET 2
9
D2
11
CLOCK 2
14 VDD
13 Q2
12 Q2
11 CLOCK 2
10 RESET 2
9 D2
8 SET 2
VDD
14
F/F1
2
Q1
1
Q1
F/F2
12
Q2
13
Q2
Description
CD4013BMS consists of two identical, independent data
type flip-flops. Each flip-flop has independent data, set,
reset, and clock inputs and Q and Q outputs. These devices
can be used for shift register applications, and, by
connecting Q output to the data input, for counter and toggle
applications. The logic level present at the D input is
transferred to the Q output during the positive going
transition of the clock pulse. Setting or resetting is
independent of the clock and is accomplished by a high level
on the set or reset line, respectively.
The CD4013BMS is supplied in these 14 lead outline pack-
ages:
10
RESET 2
7
VSS
Braze Seal DIP H4Q
Frit Seal DIP
H1B
Ceramic Flatpack H3W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-62
File Number 3080

1 page




CD4013BMS pdf
Specifications CD4013BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
VNTH VDD = 10V, ISS = -10µA
VPTH VSS = 0V, IDD = 10µA
VPTH VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
TEMPERATURE
+25oC
MIN
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 0.2µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
7-66

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