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PDF AT88SC1608 Data sheet ( Hoja de datos )
| Número de pieza | AT88SC1608 | |
| Descripción | Secure Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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1. Features
• One 128 x 8 (1K bit) Configuration Zone
• Eight 256 x 8 (16K bits) User Zones
• Low Voltage Operation: 2.7V to 5.5V
• Two-wire Serial Interface
• 16-byte Page Write Mode
• Self-timed Write Cycle (10 ms max)
• Answer-to-Reset Register
• High Security Memory Including Anti-wiretapping
– 64-bit Authentication Protocol (under exclusive patent license from ELVA)
– Authentication Attempts Counter
– Eight Sets of Two 24-bit Passwords
– Specific Passwords for Read and Write
– Sixteen Password Attempts Counters
– Selectable Access Rights by Zone
• ISO Compliant Packaging
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 100 Years
– ESD Protection: 4,000V (min)
• Low-power CMOS
Table 1-1.
Name
VCC
GND
SCL
SDA
RST
Pin Configuration
Description
Supply Voltage
Ground
Serial Clock Input
Serial Data Input/Output
Reset Input
ISO Module Contact
C1
C5
C3
C7
C2
Card Module Contact8-pin SOIC or PDIP
VCC
NC
GND
NC
SDA
NC
1
2
3
4
Standard Package Pin
8
1
6
3
7
8 VCC
7 RST
6 SCL
5 NC
8 x 256 x 8
Secure Memory
with
Authentication
AT88SC1608
2. Description
The AT88SC1608 provides 17,408 bits of serial
EEPROM memory organized as one configuration zone
of 128 bytes and eight user zones of 256 bytes each.
This device is optimized as a “secure memory” for the
smart card market, secure identification for electronic
data transfer, or components in a system, without the
requirement of an internal microprocessor.
0971H–SMEM–6/08
1 page  
AT88SC1608
Table 5-2. Configuration Zone
Configuration
$0 $1 $2 $3 $4 $5 $6
Fabrication
Answer-to-Reset
Fab Code
Reserved
Lot History Code
Card Manufacturer Code
Access
AR0 AR1 AR2 AR3 AR4 AR5
Reserved for Future Use
AR6
Authentication
AAC
Identification Number (Nc)
Cryptogram (Ci)
Secret
Secret Seed (Gc)
Test Reserved for Memory Test
PAC Write 0 PAC Read 0
PAC Write 1 PAC Read 1
PAC Write 2 PAC Read 2
Passwords
PAC
Write 3
PAC
Read 3
PAC Write 4 PAC Read 4
PAC Write 5 PAC Read 5
PAC Write 6 PAC Read 6
Note:
PAC Secure Code/Write 7
AAC: Authentication Attempts Counter
PAC: Password Attempts Counter
AR0−7: Access Register for User Zone 0 to 7
PAC
Read 7
$7
AR7
$00
$08
$10
$18
$20
$28
$30
$38
$40
$48
$50
$58
$60
$68
$70
$78
0971H–SMEM–6/08
5
5 Page 
AT88SC1608
10.4 Read Fuses
Figure 10-4. Read Fuses
S
T
A
R
T Command
Fuses Add
NS
AT
CO
KP
10110101
10000000
A
C
K
0 0 0 0 0 F2 F1 F0
A
C
K
Note: Fx = 1: fuse is not blown
Fx = 0: fuse is blown
The read fuses operation is always allowed. The device only transmits one data byte and waits
for a new command.
10.5 Write Fuses
Figure 10-5. Write Fuses
S
T
A
R
T Command
Fuses Add
S
T
O
P
10110100 10000000
AA
CC
KK
The write fuses operation is only allowed under secure code control and no data byte is transmit-
ted by the host. The fuses are blown sequentially: CMA is blown if FAB is equal to “0”, and PER
is blown if CMA is equal to “0”. If the fuses are all “0”s, the operation is canceled and the device
waits for a new command.
Once a stop condition is issued to indicate the end of the host’s write operation, the device ini-
tiates the internal nonvolatile write cycle. An ACK polling sequence can be initiated immediately.
Once blown, these fuses cannot be reset.
10.6
Answer-to-reset
If RST is high during SCL clock pulse, the reset operation occurs according to the ISO 7816-10
synchronous answer-to-reset. The four bytes of the answer-to-reset register are transmitted
least significant bit (LSB) first on the 32 clock pulses provided on SCL. Following a RST asser-
tion, all password and authentication access privileges are reset.
The values programmed by Atmel are shown in Figure 10-6 below.
0971H–SMEM–6/08
11
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| PDF Descargar | [ Datasheet AT88SC1608.PDF ] | |
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