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PDF HI-1582 Data sheet ( Hoja de datos )
| Número de pieza | HI-1582 | |
| Descripción | 3.3V Single Transceiver | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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February 2016
DESCRIPTION
The HI-1582 low power CMOS transceiver is designed to
meet the requirements of the MIL-STD-1553 and MIL-
STD-1760 specifications. It is a pin-compatible, form and fit
drop-in replacement for the Data Device Corporation MIL-
STD-1553 transceiver, BU-63133L8.
The transmitter section of each bus takes complementary
CMOS / TTL Manchester II bi-phase data and converts it to
differential voltages suitable for driving the bus isolation
transformer. A transmitter inhibit control signal is provided.
The receiver section converts the 1553 bus bi-phase data
to complementary CMOS / TTL data suitable for input to a
Manchester decoder. The receiver has a separate enable
input pin, STROBE, which, when low, forces the receiver
outputs to logic "0".
The HI-1582 is packaged in a 32-pin plastic chip-carrier
package (QFN) with an integral exposed heatsink on the
package bottom. The heatsink may be soldered to the PCB
ground plane for optimal thermal dissipation. The HI-1582
is available in industrial (-40°C to +85°C) or extended
(-55°C to +125°C) temperature range options.
HI-1582
MIL-STD-1553 / MIL-STD-1760
3.3V Single Transceiver
PIN CONFIGURATIONS
TX DATA OUT 1
VCC 2
GROUND 3
SLEEP 4
-5
-6
VCC 7
RX DATA 8
1582PCI
1582PCT
24 -
23 TX DATA OUT
22 VCC
21 GROUND
20 TX DATA IN
19 TX DATA IN
18 TX INHIBIT
17 RX DATA IN
32 Pin Plastic 7mm x 7mm
Chip-scale package
FEATURES
! Compliant to MIL-STD-1553A and B,
MIL-STD-1760 and ARINC 708A
! 3.3V single supply operation
! Small 7mm x 7mm 32-pin plastic chip-scale
package
! Less than 0.5W maximum power dissipation
! Single Transceiver allows full dual redundancy
! Drop in replacement for Data Device
Corporation BU-63133L8
(DS1582 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
02/16
1 page  
HI-1582
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
Total Supply Current
SYMBOL
VDD
ICC1
CONDITION
Not Transmitting
MIN TYP
3.0 3.3
4
ICC2
Transmit @ 100% duty cycle
800
Transformer coupled
70 Ohm resistive load
Power Dissipation
PD1
Not Transmitting
PD2
Transmit @ 100% duty cycle
Transformer coupled
70 Ohm resistive load
15
0.3
Min. Input Voltage (Logic 1)
VIH
Digital inputs
70%
Max. Input Voltage (Logic 0)
VIL Digital inputs
Input Current (Logic 1)
IIH
TX DATA IN, TX DATA IN, TX INHIBIT, SLEEP
20
STROBE
Max. Input Current (Logic 0)
IIL
TX DATA IN, TX DATA IN, TX INHIBIT, SLEEP
-20
STROBE
-100
Min. Output Voltage (Logic 1)
VOH IOUT = -2.0mA, Digital outputs VCC - 0.4
Max. Output Voltage (Logic 0)
VIH IOUT = 2.0mA, Digital outputs
RECEIVER
(Measured at Point “AD“ in Figure 5 unless otherwise specified)
Input resistance
RIN
Differential (at chip pins)
20
Input capacitance
CIN Differential
Common mode rejection ratio
CMRR
40
Input Level
VIN Differential
Input common mode voltage
VICM
-10.0
Threshold Voltage - Direct-coupled
Detect
VTHD
1.15
Measured at Point “AD” in Figure 5 using
Pulse outputs present
1 Mhz sinusoid across 35 Ohm load
at RX DATA OUT / RX DATA OUT
No Detect
VTHND
No pulse outputs
at RX DATA OUT / RX DATA OUT
Threshold Voltage - Transformer-coupled Detect
Measured at Point “AT” in Figure 6 using
1 Mhz sinusoid across 70 Ohm load
No Detect
VTHD
VTHND
Pulse outputs present
at RX DATA OUT/RX DATA OUT
No pulse outputs
at RX DATA OUT / RX DATA OUT
0.86
MAX
3.6
10
900
UNITS
V
mA
mA
60 mW
0.5 W
30%
100
20
-20
0.4
VCC
VCC
µA
µA
µA
µA
V
V
5
9
10.0
Kohm
pF
dB
Vp-p
V-pk
Vp-p
0.28
Vp-p
Vp-p
0.20
Vp-p
HOLT INTEGRATED CIRCUITS
5
5 Page 
PACKAGE DIMENSIONS
32-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)
(70..020706)BSC
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
power plane for optimum
thermal dissipation.
7.000
(0.276)
BSC
Top View
5.400 ± 0.050
(0.213 ± 0.002)
millimeters (inches)
Package Type: 32PCS7
5.400 ± 0.050
(0.213 ± 0.002)
Bottom
View
0.65
(0.026)
BSC
0.300
(0.012) typ
1.00
(0.039)
max
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
0.200
(0.008)
typ
0.400 ± 0.050
(0.016 ± 0.002)
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HI-1582.PDF ] | |
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