PDF HI-3210 Data sheet ( Hoja de datos )

Número de pieza	HI-3210
Descripción	Octal Receiver / Quad Transmitter
Fabricantes	HOLTIC
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No Preview Available ! August 2013 HI-3210 ARINC 429 DATA MANAGEMENT ENGINE / Octal Receiver / Quad Transmitter GENERAL DESCRIPTION The HI-3210 from Holt Integrated Circuits is a single chip CMOS data management IC capable of managing, storing and forwarding avionics data messages between eight ARINC 429 receive channels and four ARINC 429 transmit channels. The ARINC 429 buses may be operated independently, allowing a host CPU to send and receive data on multiple buses, or the HI-3210 can be programmed to automati- cally re-format, re-label, re-packetize and re-transmit data from ARINC 429 receive buses to ARINC 429 transmit buses. A 32K x 8 on-board memory allows received data to be logically organized and automatically updated as new ARINC 429 labels are received. An auto-initialization feature allows configuration informa- tion to be up-loaded from an external EEPROM on reset to facilitate rapid start-up or operation without a host CPU. The HI-3210 interfaces directly with Holt’s HI-8448 octal ARINC 429 receiver IC and HI-8592 or HI-8596 ARINC 429 line drivers. FEATURES · Eight ARINC 429 Receive channels · Four ARINC 429 Transmit channels · 32KB on chip user-configurable data storage memory · Programmable received data filtering · Programmable transmission schedulers for periodic ARINC 429 broadcasting · SPI Host CPU interface · Auto-initialization feature allows power-on configuration or independent operation without CPU PIN CONFIGURATION APPLICATION CPU Memory Controller HI-3210 AACK 1 ARXBIT6 2 AINT 3 ARXBIT7 4 SCANSHIFT 5 ARX2N 6 ARX3P 7 VDD 8 GND 9 ARX3N 10 ARX4P 11 ARX4N 12 ARX5P 13 ARX5N 14 ARX6P 15 ARX6N 16 HI-3210PQI & HI-3210PQT 48 ARXBIT3 47 ATXSLP0 46 ATX0N 45 ATX0P 44 ATX1N 43 ATX1P 42 ATXSLP1 41 VDD 40 GND 39 ARXBIT2 38 ATXSLP2 37 ATX2N 36 ATX2P 35 ATX3N 34 ATX3P 33 ATXSLP3 64 - Pin Plastic Quad Flat Pack (PQFP) (See ordering information for additional pin configurations) (DS3210 Rev. D) 08/13 1 page HI-3210 Example 5. Autonomous ARINC 429 Data Concentrator / Repeater 8 x ARINC 429 Receive Buses RECEIVER 7 RECEIVER 6 RECEIVER 5 RECEIVER 4 RECEIVER 3 RECEIVER 2 RECEIVER 1 RECEIVER 0 Channel 7, Label FF “ “ “ Channel 7, Label 01 Channel 7, Label 00 Channel 6, Label FF “ “ “ Channel 6, Label 01 Channel 6, Label 00 Channel 5, Label FF “ “ “ Channel 5, Label 01 Channel 5, Label 00 Channel 4, Label FF “ “ “ Channel 4, Label 01 Channel 4, Label 00 Channel 3, Label FF “ “ “ Channel 3, Label 01 Channel 3, Label 00 Channel 2, Label FF “ “ “ Channel 2, Label 01 Channel 2, Label 00 Channel 1, Label FF “ “ “ Channel 1, Label 01 Channel 1, Label 00 Channel 0, Label FF “ “ “ Channel 0, Label 01 Channel 0, Label 00 Descriptor Table 3 TRANSMIT SCHEDULER 3 TRANSMITTER 3 TRANSMIT TIMER Descriptor Table 2 TRANSMIT SCHEDULER 2 TRANSMITTER 2 TRANSMIT TIMER Descriptor Table 1 TRANSMIT SCHEDULER 1 TRANSMITTER 1 TRANSMIT TIMER Descriptor Table 0 TRANSMIT SCHEDULER 0 TRANSMITTER 0 TRANSMIT TIMER 4 x ARINC 429 Transmit Buses EEPROM SPI HI-3210 Auto-Initialization EEPROM HOLT INTEGRATED CIRCUITS 5 5 Page HI-3210 HI-3210 Operational Status Information The Master Status Register may be read at any time to determine the current operational state of the HI-3210: MASTER STATUS REGISTER (Address 0x800E) XX 76543210 MSB LSB Bit Name R/W Default Description 7 READY R 0 This bit is high, when the READY output pin is high, indicating that the part is able to accept and respond to host CPU SPI commands 6 ACTIVE R 0 This bit is high after RUN is asserted and the HI-3210 is in normal operating mode. 5 SAFE R 0 This bit goes high when the part enters safe mode as a result of a Built-in Self-test fail or auto- initialization fail. 4 RAM BUSY R 0 This is high during the time the RAM Integrity Check is running and RAM is clearing 3 PROG R 0 Indicates that the HI-3210 is currently in the EEPROM programming cycle. Note that READY stays low until the cycle is complete. 2 AUTOINIT R 0 The HI-3210 is currently loading internal memory, registers and look-up tables from the Auto- initialization EEPROM 1- R 0 Not used 0- R 0 Not Used HOLT INTEGRATED CIRCUITS 11 11 Page

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