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PDF HI-3584 Data sheet ( Hoja de datos )
| Número de pieza | HI-3584 | |
| Descripción | 3.3V Serial Transmitter and Dual Receiver | |
| Fabricantes | HOLTIC | |
| Logotipo |  |
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April 2013
HI-3584
Enhanced ARINC 429
3.3V Serial Transmitter and Dual Receiver
GENERAL DESCRIPTION
The HI-3584 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a 16-bit parallel data bus to the
ARINC 429 serial bus. The HI-3584 design offers many
enhancements to the industry standard HI-8282
architecture. The device provides two receivers each with
label recognition, a 32 by 32 FIFO, and an analog line
receiver. Up to 16 labels may be programmed for each
receiver. The independent transmitter also has a 32 by 32
FIFO. The status of all three FIFOs can be monitored using
the external status pins or by polling the HI-3584’s status
register.
Other new features include a programmable option of data
or parity in the 32nd bit, and the ability to unscramble the 32
bit word. Also, versions are available with different values
of input resistance to allow users to more easily add
external lightning protection circuitry.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The databus and all control
signals are CMOS and TTL compatible.
The HI-3584 applies the ARINC protocol to the receivers
and transmitter. Timing is based on a 1 Megahertz clock.
Additional interface circuitry such as the Holt HI-8585 or
HI-8586 is required to translate the transmitter’s 3.3 volt
logic outputs to ARINC 429 drive levels.
FEATURES
! ARINC specification 429 compatible
! 3.3V logic supply operation
! Dual receiver and transmitter interface
! Analog line receivers connect directly to ARINC bus
! Programmable label recognition
! On-chip 16 label memory for each receiver
! 32 x 32 FIFOs each receiver and transmitter
! Independent data rate selection for transmitter
and each receiver
! Status register
! Data scramble control
! 32nd transmit bit can be data or parity
! Self test mode
! Low power
! Industrial & full military temperature ranges
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
PIN CONFIGURATIONS (Top View)
(See page 13 for additional pin configuration)
See Note below
N/C - 1
D/R1 - 2
FF1 - 3
HF1 - 4
D/R2 - 5
FF2 - 6
HF2 - 7
SEL - 8
EN1 - 9
EN2 - 10
N/C - 11
BD15 - 12
BD14 - 13
BD13 - 14
BD12 - 15
BD11 - 16
HI-3584PCI
&
HI-3584PCT
48 - CWSTR
47 - ENTX
46 - 429DO
45 - N/C
44 - N/C
43 - N/C
42 - N/C
41 - 429DO
40 - FFT
39 - HFT
38 - TX/R
37 - PL2
36 - PL1
35 - BD00
34 - BD01
33 - N/C
(Note: All 3 VDD pins must be connected to the same 3.3V supply)
64 - Pin Plastic 9mm x 9mm
Chip-Scale Package
FF1 - 1
HF1 - 2
D/R2 - 3
FF2 - 4
HF2 - 5
SEL - 6
EN1 - 7
EN2 - 8
BD15 - 9
BD14 - 10
BD13 - 11
BD12 - 12
BD11 - 13
HI-3584PQI
&
HI-3584PQT
39 - N/C
38 - CWSTR
37 - ENTX
36 - N/C
35 - 429DO
34 - 429DO
33 - N/C
32 - FFT
31 - HFT
30 - TX/R
29 - PL2
28 - PL1
27 - BD00
52 - Pin Plastic Quad Flat Pack (PQFP)
(DS3584 Rev. G)
HOLT INTEGRATED CIRCUITS
www.holtic.com
04/13
1 page  
HI-3584
FUNCTIONAL DESCRIPTION (cont.)
RECEIVER PARITY
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is
received from the incoming ARINC word.
Odd Parity Received
The parity bit is reset to indicate correct parity was received
and the resulting word is written to the receive FIFO.
Even Parity Received
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be “0” when valid (odd parity) ARINC 429 words are received.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending upon the state of control
register bits CR2-CR11, the received ARINC 32-bit word is then
checked for correct decoding and label matching before being
loaded into the 32 x 32 receive FIFO. ARINC words which do not
meet the necessary 9th and 10th ARINC bit or label matching are
ignored and are not loaded into the receive FIFO. The following
table describes this operation.
CR2(3) ARINC word CR6(9) ARINC word
matches
bits 9,10
label
match
CR7,8 (10,11)
0 X0 X
1 No 0
X
1 Yes 0
X
0 X 1 No
0 X 1 Yes
1 Yes 1
No
1 No 1 Yes
1 No 1 No
1 Yes 1 Yes
FIFO
Load FIFO
Ignore data
Load FIFO
Ignore data
Load FIFO
Ignore data
Ignore data
Ignore data
Load FIFO
HOLT INTEGRATED CIRCUITS
5
5 Page 
TIMING DIAGRAMS (cont.)
HI-3584
PL2
TXR
ENTX
429DO
tPL2EN
TRANSMITTING DATA
tENDAT
ARINC BIT
DATA
BIT 1
ARINC BIT
DATA
BIT 2
tDTX/R
ARINC BIT
DATA
BIT 32
429DO
One Null Zero Null
One
Null
RIN
D/R
EN
SEL
PL1
PL2
TXR
BIT 32
tD/R
tD/REN
tSELEN
DON'T CARE
tENPL
tEN
ENTX
429DO
429DO
REPEATER OPERATION TIMING
tENEN
tEND/R
tEN
tENSEL
tPLEN
tENPL
tSELEN
DON'T CARE
tENSEL
tPLEN
tTX/REN
tTX/R
tENDAT
BIT 1
tENTX/R
tDTX/R
BIT 32
tENTX/R
tNULL
HOLT INTEGRATED CIRCUITS
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet HI-3584.PDF ] | |
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