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CD40208BMS fiches techniques PDF

Intersil Corporation - CMOS 4 x 4 Multiport Register

Numéro de référence CD40208BMS
Description CMOS 4 x 4 Multiport Register
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CD40208BMS fiche technique
CD40208BMS
December 1992
CMOS 4 x 4 Multiport Register
Features
Description
• High Voltage Types (20V Rating)
• One Input and Two Output Buses
• Unlimited Expansion in Bit and Word Directions
• Data Lines have Latched Inputs
• 3-State Outputs
• Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of any of Four Registers on Bus
A and Bus B and Independent Writing Into any of the
Four Registers
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Stan-
dards No. 13B, “Standard Specifications for Descrip-
tion of “B” Series CMOS Devices”
Applications
• Scratch Pad Memories
• Arithmetic Units
• Data Storage
The CD40208BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high imped-
ance state. The high impedance third state provides the out-
puts with the capability of being connected to the bus lines in
a bus organized system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
The CD40208BMS types are supplied in hermetic 24-lead
dual-in-line ceramic packages (D and F suffixes), 24-lead
dual-in-line plastic packages (E suffix), 24-lead ceramic flat
packages (K suffix), and in chip form (H suffix).
The CD40208BMS is supplied in these 24-lead outline pack-
ages:
Braze Seal DIP
HNZ
Ceramic Flatpack H4P
Pinout
CD40208BMS
TOP VIEW
Q3B 1
Q2B 2
ENABLE A 3
Q0A 4
Q1A 5
Q2A 6
Q3A 7
WRITE 0 8
WRITE 1 9
READ 0B 10
READ 1B 11
VSS 12
24 VDD
23 Q1B
22 Q0B
21 ENABLE B
20 D0
19 D1
18 D2
17 D3
16 CLOCK
15 WRITE ENABLE
14 READ 1A
13 READ 0A
Functional Diagram
WRITE
ENABLE
ENABLE A
DATA
INPUTS
20
D0
19
D1
18
D2
17
D3
15 3
4
Q0
5
Q1
6
Q2
7
Q3
WRITE 0
WRITE 1
8
9
14
READ 1A
13
READ 0A
11
READ 1B
10
READ 0B
22
Q0
23
Q1
2
Q2
1
Q3
VDD = 24
VSS = 12
16 21
CLOCK ENABLE B
WORD A
OUTPUT
WORD B
OUTPUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1431
File Number 3396

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