|
|
PDF AD9215 Data sheet ( Hoja de datos )
| Número de pieza | AD9215 | |
| Descripción | 3V A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD9215 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Data Sheet
FEATURES
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to pro-
vide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold ampli-
fier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with pow-
er and cost savings over previously available ADCs, the AD9215
is suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement for-
mats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
10-Bit, 65/80/105 MSPS,
3 V A/D Converter
AD9215
FUNCTIONAL BLOCK DIAGRAM
AVDD
DRVDD
VIN+
VIN–
SHA
PIPELINE
ADC CORE
REFT
REFB
AD9215
CORRECTION LOGIC
10
OUTPUT BUFFERS
VREF
SENSE
REF
SELECT
CLOCK
DUTY CYCLE
STABLIZER
0.5V
MODE
SELECT
OR
D9 (MSB)
D0
AGND
CLK
PDWN
Figure 1.
MODE DGND
Fabricated on an advanced CMOS process, the AD9215 is avail-
able in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accom-
modate 2.5 V and 3.3 V logic families.
2. Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be config-
ured for single-ended or differential operation.
4. The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
5. The clock duty cycle stabilizer maintains converter per-
formance over a wide range of clock pulse widths.
6. The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9215
Data Sheet
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR (AIN = –7 dBFS)
fIN1 = 70.3 MHz, fIN2 = 71.3 MHz
fIN1 = 100.3 MHz, fIN2 = 101.3 MHz
ANALOG BANDWIDTH
Temp
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
VI
I
VI
I
V
V
V
V
V
AD9215BRU-65/ AD9215BRU-80/ AD9215BRU-105/
AD9215BCP-65 AD9215BCP-80 AD9215BCP-105
Min Typ Max Min Typ Max Min Typ Max
56.0 58.5
57.0 59.0
56.0 58.0
56.5 58.5
56.0 58.5
57.0 59.0
56.0 58.0
56.5 58.5
58.0
57.5
57.5
56.6 58.5
57.5
56.4 58.0
57.8
57.7
55.8 58.5
56.5 59.0
55.8 58.0
56.3 58.5
55.7 58.5
56.8 58.5
55.5 58.0
56.3 58.5
56.0
55.5
57.6
56.5 58.2
57.3
56.1 57.8
57.7
57.4
9.1 9.5
9.2 9.6
9.1 9.4
9.1 9.5
9.0 9.5
9.3 9.5
9.0 9.4
9.0 9.5
9.1
9.0
9.3
9.2 9.5
9.4
9.1 9.4
9.4
9.3
−78 −64
−80 −65
−77 −64
−78 −65
−78 −64
−80 −65
−76 −63
−78 −65
−70
−70
−78
−84 −70
−74
−75 −61
−75
−74
−77 −67
−78 −68
−77 −67
−78 −68
−77 −66
−77 −68
−77 −66
−77 −68
−80
−80
−73
−75 −66
−71
−75 −63
-75
−75
75 75
74 74
300 300 300
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
1 Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105.
Rev. B | Page 4 of 36
5 Page 
AD9215
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V, unless
otherwise noted.
0
AIN = –0.5dBFS
SNR = 58.0
–20 ENOB = 9.4 BITS
SFDR = 75.5dB
80
2V p-p SFDR (dBc)
AIN = –0.5dBFS
75
–40 70
1V p-p SFDR (dBc)
–60 65
–80 60 2V p-p SNR (dB)
–100
–120
0
6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.50
FREQUENCY (MHz)
Figure 9. Single-Tone 32k FFT with fIN = 10.3 MHZ, fSAMPLE = 105 MSPS
0
AIN = –0.5dBFS
SNR = 57.8
–20 ENOB = 9.4 BITS
SFDR = 75.0dB
–40
–60
–80
–100
–120
0
6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.50
FREQUENCY (MHz)
Figure 10. Single-Tone 32k FFT with fIN = 70.3 MHz, fSAMPLE = 105 MSPS
0
AIN = –0.5dBFS
SNR = 57.7
–20 ENOB = 9.3 BITS
SFDR = 75dB
–40
–60
–80
–100
–120
0
6.56 13.13 19.69 26.25 32.81 39.38 45.94 52.50
FREQUENCY (MHz)
Figure 11. Single-Tone 32k FFT with fIN = 100.3 MHz, fSAMPLE = 105 MSPS
55
1V p-p SNR (dB)
50
5 15 25 35 45 55 65 75 85
ENCODE (MSPS)
Figure 12. AD9215-80 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
80
2V p-p SFDR (dBc)
AIN = –0.5dBFS
75
70 1V p-p SFDR (dBc)
65
60 2V p-p SNR (dB)
55
1V p-p SNR (dB)
50
5 15 25 35 45 55 65
ENCODE (MSPS)
Figure 13. AD9215-65 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
85
2V p-p SFDR
80
75
70
65
60
2V p-p SNR
55
0 20 40 60 80 100
fSAMPLE (MSPS)
Figure 14. AD9215-105 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Rev. B | Page 10 of 36
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9215.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD9211 | 1.8 V Analog-to-Digital Converter | Analog Devices |
| AD9212 | Serial LVDS A/D Converter | Analog Devices |
| AD9214 | 3V A/D Converter | Analog Devices |
| AD9215 | 3V A/D Converter | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |