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PDF AD9218 Data sheet ( Hoja de datos )
| Número de pieza | AD9218 | |
| Descripción | 3V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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10-Bit, 40/65/80/105 MSPS
3 V Dual Analog-to-Digital Converter
AD9218
FEATURES
Dual 10-bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC
Low power: 275 mW at 105 MSPS per channel
On-chip reference and track-and-hold
300 MHz analog bandwidth each channel
SNR = 57 dB @ 41 MHz, Encode = 80 MSPS
1 V p-p or 2 V p-p analog input range each channel
3.0 V single-supply operation (2.7 V to 3.6 V)
Power-down mode for single-channel operation
Twos complement or offset binary output mode
Output data alignment mode
Pin compatible with the 8-bit AD9288
–75 dBc crosstalk between channels
APPLICATIONS
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
I and Q communications
Ultrasound equipment
GENERAL DESCRIPTION
The AD9218 is a dual 10-bit monolithic sampling analog-to-
digital converter with on-chip track-and-hold circuits. The
product is low cost, low power, and is small and easy to use. The
AD9218 operates at a 105 MSPS conversion rate with
outstanding dynamic performance over its full operating range.
Each channel can be operated independently.
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
supply and a clock for full operation. No external reference or
driver components are required for many applications. The
digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or
2.5 V logic.
The clock input is TTL/CMOS compatible and the 10-bit digital
outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies.
User-selectable options offer a combination of power-down
modes, digital data formats, and digital data timing schemes.
In power-down mode, the digital outputs are driven to a high
impedance state.
FUNCTIONAL BLOCK DIAGRAM
ENCODE A
AINA
AINA
REFINA
REFOUT
REFINB
AINB
AINB
ENCODE B
TIMING
T/H
T/H
TIMING
AD9218
ADC
/
10
OUTPUT
REGISTER
/
10
REF
ADC
/
10
OUTPUT
REGISTER
/
10
D9A TO D0A
USER
SELECT NO. 1
USER
SELECT NO. 2
DATA
FORMAT/
GAIN
D9B TO D0B
VD GND VDD
Figure 1.
PRODUCT HIGHLIGHTS
1. Low Power. Only 275 mW power dissipation per channel
at 105 MSPS. Other speed grades proportionally scaled
down while maintaining high ac performance.
2. Pin Compatibility Upgrade. Allows easy migration from 8-bit
to 10-bit devices. Pin compatible with the 8-bit AD9288
dual ADC.
3. Easy to Use. On-chip reference and user controls provide
flexibility in system design.
4. High Performance. Maintains 54 dB SNR at 105 MSPS
with a Nyquist input.
5. Channel Crosstalk. Very low at –75 dBc.
6. Fabricated on an Advanced CMOS Process. Available in a
48-lead low profile quad flat package (7 mm × 7 mm
LQFP) specified over the industrial temperature range
(−40°C to +85°C).
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD9218
DIGITAL SPECIFICATIONS
VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.
Table 2.
Parameter
DIGITAL INPUTS
Encode Input Common
Mode
Encode 1 Voltage
Encode 0 Voltage
Encode Input Resistance
Logic 1 Voltage—S1, S2,
DFS
Logic 0 Voltage—S1, S2,
DFS
Logic 1 Current—S1
Logic 0 Current—S1
Logic 1 Current—S2
Logic 0 Current—S2
Logic 1 Current—DFS
Logic 0 Current—DFS
Input Capacitance—S1,
S2, Encode Inputs
Input Capacitance DFS
DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
Output Coding
Test
Temp Level Min
AD9218BST-40/-65
Typ Max
Full V
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
Full VI
25°C V
25°C V
Full VI
Full VI
2
1.8
2
–50
–400
50
–50
30
–400
VD/2
2.0
±0
–230
230
±0
100
–230
2
4.5
0.8
2.3
0.8
50
–50
400
50
200
–50
2.45
0.05
Twos complement or offset binary
AD9218BST-80/-105
Min Typ Max
Unit
2
1.8
2
–50
–400
50
–50
30
–400
VD/2
0.8
2.0 2.3
±0
–230
230
±0
100
–230
2
4.5
0.8
50
–50
400
50
200
–50
V
V
V
kΩ
V
V
μA
μA
μA
μA
μA
μA
pF
pF
2.45 V
0.05 V
Twos complement or offset binary
Rev. C | Page 4 of 28
5 Page 
AD9218
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level signal
(–40 dBFS) when the adjacent interfering channel is driven by a
full-scale signal.
Differential Analog Input Resistance,
Differential Analog Input Capacitance,
Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180
degrees out of phase. Peak-to-peak differential is computed by
rotating the input phase 180 degrees and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
The effective number of bits is calculated from the measured
SNR based on the equation
ENOB = SNRMEASURED − 1.76 dB
6.02
ENCODE Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a given clock rate, these specifications
define an acceptable ENCODE duty cycle.
Full-Scale Input Power
Expressed in dbm. Computed using the following equation:
⎜⎛ VFull−Scale 2 rms ⎟⎞
⎜
PowerFull−Scale = 10 log⎜
⎜
Z INPUT
0.001
⎟
⎟
⎟
⎜⎟
⎝⎠
Gain Error
Gain error is the difference between the measured and the ideal
full-scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% level crossing of ENCODE A or
ENCODE B and the 50% level crossing of the respective
channel’s output data bit.
Noise (for Any Range Within the ADC)
VNOISE =
Z × 0.001×10⎜⎛ FSdBm − SNRdBc − SignaldBFS ⎟⎞
⎝ 10 ⎠
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and Signal is the signal level within the ADC
reported in dB below full scale. This value includes both
thermal and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Rev. C | Page 10 of 28
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet AD9218.PDF ] | |
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