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PDF LC72131K Data sheet ( Hoja de datos )
| Número de pieza | LC72131K | |
| Descripción | PLL Frequency Synthesizer | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA0788A
LC72131K
LC72131KMA
CMOS IC
PLL Frequency Synthesizer
Overview
The LC72131K and LC72131KMA are PLL frequency synthesizers for use in tuners in radio/cassette players.
They allow high-performance AM/FM tuners to be implemented easily.
Features
• High speed programmable dividers
• FMIN: 10 to 160MHz …………………….. pulse swallower (built-in divide-by-two prescaler)
• AMIN: 2 to 40MHz ………………………. pulse swallower
0.5 to 10MHz …………………….. direct division
• IF counter
• IFIN: 0.4 to 12MHz ………………………. AM/FM IF counter
• Reference frequencies
• Twelve selectable frequencies (4.5 or 7.2MHz crystal)
• 100, 50, 25, 15, 12.5, 6.25, 3.125, 10, 9, 5, 3, 1kHz
• Phase comparator
• Dead zone control
• Unlock detection circuit
• Deadlock clear circuit
• Built-in MOS transistor for forming an active low-pass filter
• I/O ports
• Dedicated output ports: 4 • Input or output ports: 2 • Support clock time base output
• Serial data I/O
• Support CCB format communication with the system controller.
Continued on next page.
• CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
• CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
June, 2013
O3112HK 20120919-S00009/51407HKIM 20070328-S00008,S00009 No.A0788-1/22
1 page  
Serial Data Timing
LC72131K, LC72131KMA
CE
tCH tCL
CL VVIIHL
VIH
DI
VIH
VIL tSU
tHD VIL
DO
VIH
VIL
tEL
VIH
tES
VIL
tDC tDC
Internal
data latch
VIL
VIH
tEH
tDH
tLC
Old New
When stopped with CL low
CE VIH
tCH tCL
CL VVIIHL
VIH
DI
VIH
VIH tEL
VIL
tES
VIL tSU
tHD VIL
DO
tDC
Internal
data latch
VIL
VIH
tEH
tDH
tLC
Old New
Package Dimensions
unit : mm (typ)
3059A [LC72131K]
21.0
22 12
When stopped with CL high
Package Dimensions
unit : mm (typ)
3445 [LC72131KMA]
12.7
20
1 11
0.95
12
(0.635)
1.27
0.4
0.15
(0.8) 1.78
0.48 SANYO : DIP22S(300mil)
SANYO : MFP20J(300mil)
No.A0788-5/22
5 Page 
LC72131K, LC72131KMA
Continued from preceding page.
No. Control block/data
(8) Phase comparator
control data
DZ0, DZ1
(9) Clock time base
TBC
(10) Charge pump control
data
DLC
Functions
• Controls the phase comparator dead zone.
DZ1 DZ0
Dead zone mode
00
01
10
11
DZA
DZB
DZC
DZD
Dead zone width: DZA<DZB<DZC<DZD
Setting TBC to one causes an 8Hz, 40% duty clock time base signal to be output from the BO1
pin. (BO1 data is invalid in this mode.)
Forcibly controls the charge pump output.
DLC
Charge pump output
0 Normal operation
1 Forced low
(11) IF counter control
data
IFS
(12) LSI test data
TEST0 to 2
(13) DNC
Note: If deadlock occurs due to the VCO control voltage (Vtune) going to zero and the VCO
oscillator stopping, deadlock can be cleared by forcing the charge pump output to low and
setting Vtune to VCC. (This is the deadlock clearing circuit.)
This data must be set 1 in normal mode.
IFS Though if this value is set to zero, the system enters input sensitivity degradation mode,
and the sensitivity is reduced to 10 to 30mVrms.
* See the “IF Counter Operation” item for details.
LSI test data
TEST0
TEST1
These values must all be set to 0.
TEST2
These test data are set to 0 automatically after the power-on reset.
Don’t care. This data must be set to 0.
Related data
BO1
DO Control Data (Serial Data Output) Structure
[3] OUT Mode
address
DI 0 1 0 1 0 1 0 0
Fist Data OUT
DO
: Must be 0.
No.A0788-11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet LC72131K.PDF ] | |
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