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Intersil Corporation - CMOS Counter/Dividers

Numéro de référence CD4022BMS
Description CMOS Counter/Dividers
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CD4022BMS fiche technique
Data Sheet
CD4017BMS, CD4022BMS
August 1998
File Number 3297
CMOS Counter/Dividers
CD4017BMS - Decade Counter with 10 Decoded Outputs
CD4022BMS - Octal Counter with 8 Decoded Outputs
CD4017BMS and CD4022BMS are 5-stage and 4-stage
Johnson counters having 10 and 8 decoded outputs, respec-
tively. Inputs include a CLOCK, a RESET, and a CLOCK INHIBIT
signal. Schmitt trigger action in the CLOCK input circuit provides
pulse shaping that allows unlimited clock input pulse rise and fall
times.
These counters are advanced one count at the positive clock sig-
nal transition if the CLOCK INHIBIT signal is low. Counter
advancement via the clock line is inhibited when the CLOCK
INHIBIT signal is high. A high RESET signal clears the counter to
its zero count. Use of the Johnson counter configuration permits
high speed operation, 2-input decode gating and spike-free
decoded outputs. Anti-lock gating is provided, thus assuring
proper counter sequence. The decoded output are normally low
and go high only at their respective decoded time slot. Each
decoded output remains high for one full clock cycle. A CARRY-
OUT signal completes one cycle every 10 clock input cycles in
the CD4017BMS or every 8 clock input cycles in the
CD4022BMS and is used to ripple-clock the succeeding device
in a multi-device counting chain.
The CD4017BMS and CD4022BMS series types are supplied in
these 16 lead outline packages
Braze Seal DIP
*H4W †H4X
Frit Seal DIP
*H1F †H1E
Ceramic Flatpack H6W
*CD4017B Only † CD4022B Only
Functional Diagrams
CD4017BMS
CLOCK
CLOCK INHIBIT
RESET
VCC = 16
VSS = 8
14 3 “0”
13 2 “1”
15 4 “2”
7 “3” DECODED
10 “4” DECIMAL
1 “5” OUT
5 “6”
6 “7”
9 “8”
11 “9”
12
CARRY OUT
CD4022BMS
CLOCK
CLOCK INHIBIT
RESET
14
13
15
VCC = 16
VSS = 8
2 “0”
1 “1”
3 “2”
7 “3” DECODED
11 “4” OUT
4 “5”
5 “6”
10 “7”
12
CARRY OUT
Features
• High Voltage Types (20V Rating)
• Fully Static Operation
• Medium-Speed Operation 10MHz (Typ) at VDD = 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
Number 13A, “Standard Specifications for Description
of ‘B’ Series CMOS Devices”
Applications
• Decade Counter/Decimal Decode Display (CD4017BMS)
• Binary Counter/Decoder
• Frequency Division
• Counter Control/Timers
• Divide-by-N Counting
• For Further Application Information, See ICAN-6166
“COS/MOS MSI Counter and Register Design and
Applications”
Pinouts
CD4017BMS
TOP VIEW
NC = NO
CONNECTION
51
12
03
24
65
76
37
VSS 8
16 VDD
15 RESET
14 CLOCK
13 CLOCK INHIBIT
12 CARRY OUT
11 9
10 4
98
CD4022BMS
TOP VIEW
NC = NO
CONNECTION
11
02
23
54
65
NC 6
37
VSS 8
16 VDD
15 RESET
14 CLOCK
13 CLOCK INHIBIT
12 CARRY OUT
11 4
10 7
9 NC
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

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